mirror of https://github.com/VLSIDA/OpenRAM.git
44 lines
1.0 KiB
Python
44 lines
1.0 KiB
Python
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#!/usr/bin/env python2.7
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"""
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Run regresion tests on a parameterized bitcell
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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OPTS = globals.OPTS
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#@unittest.skip("SKIPPING 04_pbitcell_test")
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class pbitcell_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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global verify
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import verify
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OPTS.check_lvsdrc = False
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import pbitcell
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import tech
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debug.info(2, "Bitcell with 2 write ports and 0 read ports")
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tx = pbitcell.pbitcell(num_write=2,num_read=0)
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self.local_check(tx)
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OPTS.check_lvsdrc = True
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globals.end_openram()
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# instantiate a copy of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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