mirror of https://github.com/VLSIDA/OpenRAM.git
139 lines
8.8 KiB
Plaintext
139 lines
8.8 KiB
Plaintext
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[globals/init_openram]: Initializing OpenRAM...
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[globals/setup_paths]: Temporary files saved in /home/jesse/output/
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[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/run4.py
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[globals/read_config]: Output saved in /home/jesse/openram/compiler/./
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[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
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[globals/init_paths]: Creating temp directory: /home/jesse/output/
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[verify/<module>]: Initializing verify...
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[verify/<module>]: LVS/DRC/PEX disabled.
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[characterizer/<module>]: Initializing characterizer...
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[characterizer/<module>]: Analytical model enabled.
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[globals/setup_bitcell]: Using bitcell: bitcell
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|==============================================================================|
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|========= OpenRAM v1.1.5 =========|
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|========= =========|
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|========= VLSI Design and Automation Lab =========|
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|========= Computer Science and Engineering Department =========|
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|========= University of California Santa Cruz =========|
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|========= =========|
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|========= Usage help: openram-user-group@ucsc.edu =========|
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|========= Development help: openram-dev-group@ucsc.edu =========|
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|========= Temp dir: /home/jesse/output/ =========|
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|========= See LICENSE for license info =========|
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|==============================================================================|
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** Start: 06/24/2020 00:47:16
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Technology: scn4m_subm
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Total size: 4096 bits
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Word size: 32
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Words: 128
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Banks: 1
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Write size: None
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RW ports: 1
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R-only ports: 0
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W-only ports: 0
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Netlist only mode (no physical design is being done, netlist_only=False to disable).
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DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
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DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
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Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
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[sram_config/recompute_sizes]: Recomputing with words per row: 2
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[sram_config/recompute_sizes]: Rows: 64 Cols: 64
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[sram_config/recompute_sizes]: Row addr size: 6 Col addr size: 1 Bank addr size: 7
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Words per row: 2
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Output files are:
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/home/jesse/openram/compiler/./sram_32_128_scn4m_subm.sp
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/home/jesse/openram/compiler/./sram_32_128_scn4m_subm.v
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/home/jesse/openram/compiler/./sram_32_128_scn4m_subm.lib
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/home/jesse/openram/compiler/./sram_32_128_scn4m_subm.py
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/home/jesse/openram/compiler/./sram_32_128_scn4m_subm.html
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/home/jesse/openram/compiler/./sram_32_128_scn4m_subm.log
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[dff_array/__init__]: Creating row_addr_dff rows=6 cols=1
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[dff_array/__init__]: Creating col_addr_dff rows=1 cols=1
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[dff_array/__init__]: Creating data_dff rows=1 cols=32
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[precharge_array/__init__]: Creating precharge_array
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[sense_amp_array/__init__]: Creating sense_amp_array
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[single_level_column_mux_array/__init__]: Creating single_level_column_mux_array
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[write_driver_array/__init__]: Creating write_driver_array
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[and2_dec/__init__]: Creating and2_dec and2_dec
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[and3_dec/__init__]: Creating and3_dec and3_dec
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[wordline_driver_array/__init__]: Creating wordline_driver_array
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[wordline_driver/__init__]: Creating wordline_driver wordline_driver
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[replica_bitcell_array/__init__]: Creating replica_bitcell_array 64 x 64
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[bitcell_base_array/__init__]: Creating bitcell_array 64 x 64
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[bitcell_base_array/__init__]: Creating dummy_array 1 x 64
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[bitcell_base_array/__init__]: Creating dummy_array_0 67 x 1
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[bitcell_base_array/__init__]: Creating dummy_array_1 67 x 1
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[pinvbuf/__init__]: creating pinvbuf pinvbuf
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[control_logic/__init__]: Creating control_logic_rw
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[dff_buf/__init__]: Creating dff_buf
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[dff_buf_array/__init__]: Creating dff_buf_array
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[dff_buf/__init__]: Creating dff_buf_0
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[pand2/__init__]: Creating pand2 pand2
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[pdriver/__init__]: creating pdriver pdriver
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[pbuf/__init__]: creating pbuf with size of 64
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[pdriver/__init__]: creating pdriver pdriver_0
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[pdriver/__init__]: creating pdriver pdriver_1
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[pand3/__init__]: Creating pand3 pand3
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[pdriver/__init__]: creating pdriver pdriver_2
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[pand3/__init__]: Creating pand3 pand3_0
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[pdriver/__init__]: creating pdriver pdriver_3
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[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4]
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** Submodules: 0.3 seconds
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** SRAM creation: 0.3 seconds
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SP: Writing to /home/jesse/openram/compiler/./sram_32_128_scn4m_subm.sp
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** Spice writing: 0.0 seconds
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LIB: Characterizing...
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[characterizer.lib/prepare_tables]: Loads: [ 2.45605 9.8242 39.2968 ]
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[characterizer.lib/prepare_tables]: Slews: [0.0125 0.05 0.4 ]
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[characterizer.lib/characterize_corners]: Characterizing corners: [('TT', 5.0, 25), ('SS', 5.0, 25), ('FF', 5.0, 25)]
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[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
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[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_32_128_scn4m_subm_TT_5p0V_25C.lib
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[characterizer.delay/analytical_power]: Dynamic Power: 23.657191349300003 mW
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[characterizer.delay/analytical_power]: Leakage Power: 0.004501 mW
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[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns)
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[characterizer.delay/analytical_delay]: 0.0125, 2.45605, 2.754780008429524, 0.006179820369407407
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[characterizer.delay/analytical_delay]: 0.0125, 9.8242, 2.7728289195117464, 0.00798471147762963
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[characterizer.delay/analytical_delay]: 0.0125, 39.2968, 2.8450245638406355, 0.015204275910518518
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[characterizer.delay/analytical_delay]: 0.05, 2.45605, 2.754780008429524, 0.006179820369407407
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[characterizer.delay/analytical_delay]: 0.05, 9.8242, 2.7728289195117464, 0.00798471147762963
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[characterizer.delay/analytical_delay]: 0.05, 39.2968, 2.8450245638406355, 0.015204275910518518
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[characterizer.delay/analytical_delay]: 0.4, 2.45605, 2.754780008429524, 0.006179820369407407
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[characterizer.delay/analytical_delay]: 0.4, 9.8242, 2.7728289195117464, 0.00798471147762963
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[characterizer.delay/analytical_delay]: 0.4, 39.2968, 2.8450245638406355, 0.015204275910518518
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[characterizer.lib/characterize_corners]: Corner: ('SS', 5.0, 25)
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[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_32_128_scn4m_subm_SS_5p0V_25C.lib
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[characterizer.delay/analytical_power]: Dynamic Power: 21.50653759027272 mW
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[characterizer.delay/analytical_power]: Leakage Power: 0.004501 mW
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[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns)
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[characterizer.delay/analytical_delay]: 0.0125, 2.45605, 3.030258009272477, 0.006797802406348149
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[characterizer.delay/analytical_delay]: 0.0125, 9.8242, 3.0501118114629215, 0.008783182625392592
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[characterizer.delay/analytical_delay]: 0.0125, 39.2968, 3.129527020224699, 0.016724703501570373
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[characterizer.delay/analytical_delay]: 0.05, 2.45605, 3.030258009272477, 0.006797802406348149
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[characterizer.delay/analytical_delay]: 0.05, 9.8242, 3.0501118114629215, 0.008783182625392592
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[characterizer.delay/analytical_delay]: 0.05, 39.2968, 3.129527020224699, 0.016724703501570373
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[characterizer.delay/analytical_delay]: 0.4, 2.45605, 3.030258009272477, 0.006797802406348149
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[characterizer.delay/analytical_delay]: 0.4, 9.8242, 3.0501118114629215, 0.008783182625392592
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[characterizer.delay/analytical_delay]: 0.4, 39.2968, 3.129527020224699, 0.016724703501570373
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[characterizer.lib/characterize_corners]: Corner: ('FF', 5.0, 25)
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[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_32_128_scn4m_subm_FF_5p0V_25C.lib
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[characterizer.delay/analytical_power]: Dynamic Power: 26.285768165888882 mW
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[characterizer.delay/analytical_power]: Leakage Power: 0.004501 mW
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[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns)
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[characterizer.delay/analytical_delay]: 0.0125, 2.45605, 2.4793020075865724, 0.0055618383324666665
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[characterizer.delay/analytical_delay]: 0.0125, 9.8242, 2.4955460275605725, 0.007186240329866667
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[characterizer.delay/analytical_delay]: 0.0125, 39.2968, 2.5605221074565723, 0.013683848319466669
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[characterizer.delay/analytical_delay]: 0.05, 2.45605, 2.4793020075865724, 0.0055618383324666665
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[characterizer.delay/analytical_delay]: 0.05, 9.8242, 2.4955460275605725, 0.007186240329866667
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[characterizer.delay/analytical_delay]: 0.05, 39.2968, 2.5605221074565723, 0.013683848319466669
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[characterizer.delay/analytical_delay]: 0.4, 2.45605, 2.4793020075865724, 0.0055618383324666665
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[characterizer.delay/analytical_delay]: 0.4, 9.8242, 2.4955460275605725, 0.007186240329866667
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[characterizer.delay/analytical_delay]: 0.4, 39.2968, 2.5605221074565723, 0.013683848319466669
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** Characterization: 0.6 seconds
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Config: Writing to /home/jesse/openram/compiler/./sram_32_128_scn4m_subm.py
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** Config: 0.0 seconds
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Datasheet: Writing to /home/jesse/openram/compiler/./sram_32_128_scn4m_subm.html
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** Datasheet: 0.0 seconds
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Verilog: Writing to /home/jesse/openram/compiler/./sram_32_128_scn4m_subm.v
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** Verilog: 0.0 seconds
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[globals/cleanup_paths]: Purging temp directory: /home/jesse/output/
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** End: 0.9 seconds
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