2018-09-13 20:03:35 +02:00
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*********************** Write_Driver ******************************
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.SUBCKT write_driver din bl br en vdd gnd
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2018-11-27 20:42:58 +01:00
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**** Inverter to conver Data_in to data_in_bar ******
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2018-11-27 20:49:08 +01:00
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* din_bar = inv(din)
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2018-11-27 20:42:58 +01:00
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M_1 din_bar din gnd gnd n W=0.8u L=0.4u
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M_2 din_bar din vdd vdd p W=1.4u L=0.4u
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**** 2input nand gate follwed by inverter to drive BL ******
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2018-11-27 20:49:08 +01:00
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* din_bar_gated = nand(en, din)
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2018-11-27 20:42:58 +01:00
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M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u
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M_4 net_7 din gnd gnd n W=1.4u L=0.4u
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M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u
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M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u
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2018-11-27 20:49:08 +01:00
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* din_bar_gated_bar = inv(din_bar_gated)
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M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u
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M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u
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2018-11-27 20:42:58 +01:00
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**** 2input nand gate follwed by inverter to drive BR******
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2018-11-27 20:49:08 +01:00
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* din_gated = nand(en, din_bar)
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2018-11-27 20:42:58 +01:00
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M_9 din_gated en vdd vdd p W=1.4u L=0.4u
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M_10 din_gated en net_8 gnd n W=1.4u L=0.4u
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M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u
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M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u
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2018-11-27 20:49:08 +01:00
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* din_gated_bar = inv(din_gated)
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M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u
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M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u
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2018-11-27 20:42:58 +01:00
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************************************************
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2018-11-27 20:49:08 +01:00
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* pull down with en enable
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2019-08-01 17:59:41 +02:00
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M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u
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M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u
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2018-11-27 20:42:58 +01:00
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.ENDS $ write_driver
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