2019-06-14 23:38:55 +02:00
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2019-06-15 00:06:04 +02:00
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*********************** "dummy_cell_6t" ******************************
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.SUBCKT dummy_cell_6t bl br wl vdd gnd
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2019-06-14 23:38:55 +02:00
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* Inverter 1
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M1000 Q Qbar vdd vdd p w=0.6u l=0.8u
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M1002 Q Qbar gnd gnd n w=1.6u l=0.4u
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* Inverter 2
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M1001 vdd Q Qbar vdd p w=0.6u l=0.8u
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M1003 gnd Q Qbar gnd n w=1.6u l=0.4u
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* Access transistors
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M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u
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M1005 Qbar wl br_noconn gnd n w=0.8u l=0.4u
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.ENDS
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