mirror of https://github.com/VLSIDA/OpenRAM.git
8 lines
128 B
Python
8 lines
128 B
Python
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process_corners = ["TT"]
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supply_voltages = [5.0]
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temperatures = [25]
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drc_name = "magic"
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lvs_name = "netgen"
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pex_name = "magic"
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