OpenRAM/compiler/tests/config_scn4m_subm.py

word_size = 1
num_words = 16

tech_name = "scn4m_subm"
process_corners = ["TT"]
supply_voltages = [5.0]
temperatures = [25]
route_supplies = True

drc_name = "magic"
lvs_name = "netgen"
pex_name = "magic"
Added scn4m_subm. Added scn4m_subm files (instead of scn4me_subm). Fixed missing cifoutput/cifinput in magic tech file and gds files. Fixed incorrect M3/via3/M4 design rules. 2018-09-13 21:53:35 +02:00			`word_size = 1`
			`num_words = 16`

			`tech_name = "scn4m_subm"`
			`process_corners = ["TT"]`
			`supply_voltages = [5.0]`
			`temperatures = [25]`
Add option for routing supplies. Off by default, but enabled in unit test config files. 2019-04-01 18:58:59 +02:00			`route_supplies = True`
Added scn4m_subm. Added scn4m_subm files (instead of scn4me_subm). Fixed missing cifoutput/cifinput in magic tech file and gds files. Fixed incorrect M3/via3/M4 design rules. 2018-09-13 21:53:35 +02:00
Specify DRC,LVS,PEX tool for scn4m 2018-09-14 00:18:30 +02:00			`drc_name = "magic"`
			`lvs_name = "netgen"`
			`pex_name = "magic"`