2019-04-26 21:21:50 +02:00
|
|
|
# See LICENSE for licensing information.
|
|
|
|
|
#
|
2022-11-30 23:50:43 +01:00
|
|
|
# Copyright (c) 2016-2022 Regents of the University of California and The Board
|
2019-06-14 17:43:41 +02:00
|
|
|
# of Regents for the Oklahoma Agricultural and Mechanical College
|
|
|
|
|
# (acting for and on behalf of Oklahoma State University)
|
|
|
|
|
# All rights reserved.
|
2019-04-26 21:21:50 +02:00
|
|
|
#
|
2022-11-27 22:01:20 +01:00
|
|
|
from openram import OPTS
|
2022-07-13 19:57:56 +02:00
|
|
|
from .hierarchical_predecode import hierarchical_predecode
|
2016-11-08 18:57:35 +01:00
|
|
|
|
2020-05-14 20:20:37 +02:00
|
|
|
|
2016-11-08 18:57:35 +01:00
|
|
|
class hierarchical_predecode3x8(hierarchical_predecode):
|
|
|
|
|
"""
|
|
|
|
|
Pre 3x8 decoder used in hierarchical_decoder.
|
|
|
|
|
"""
|
2021-03-08 23:40:36 +01:00
|
|
|
def __init__(self, name, column_decoder=False, height=None):
|
|
|
|
|
super().__init__(name, 3, column_decoder, height)
|
2016-11-08 18:57:35 +01:00
|
|
|
|
2018-08-27 19:42:40 +02:00
|
|
|
self.create_netlist()
|
2020-03-06 22:26:40 +01:00
|
|
|
if not OPTS.netlist_only:
|
2018-08-28 01:42:48 +02:00
|
|
|
self.create_layout()
|
2016-11-08 18:57:35 +01:00
|
|
|
|
2018-08-27 19:42:40 +02:00
|
|
|
def create_netlist(self):
|
2018-08-28 01:42:48 +02:00
|
|
|
self.add_pins()
|
2018-11-14 01:05:22 +01:00
|
|
|
self.add_modules()
|
2018-08-27 19:42:40 +02:00
|
|
|
self.create_input_inverters()
|
2020-03-06 22:26:40 +01:00
|
|
|
connections=[["inbar_0", "inbar_1", "inbar_2", "out_0", "vdd", "gnd"],
|
2020-11-03 15:29:17 +01:00
|
|
|
["in_0", "inbar_1", "inbar_2", "out_1", "vdd", "gnd"],
|
2020-03-06 22:26:40 +01:00
|
|
|
["inbar_0", "in_1", "inbar_2", "out_2", "vdd", "gnd"],
|
2020-11-03 15:29:17 +01:00
|
|
|
["in_0", "in_1", "inbar_2", "out_3", "vdd", "gnd"],
|
2020-03-06 22:26:40 +01:00
|
|
|
["inbar_0", "inbar_1", "in_2", "out_4", "vdd", "gnd"],
|
|
|
|
|
["in_0", "inbar_1", "in_2", "out_5", "vdd", "gnd"],
|
|
|
|
|
["inbar_0", "in_1", "in_2", "out_6", "vdd", "gnd"],
|
|
|
|
|
["in_0", "in_1", "in_2", "out_7", "vdd", "gnd"]]
|
|
|
|
|
self.create_and_array(connections)
|
2016-11-08 18:57:35 +01:00
|
|
|
|
2020-03-06 22:26:40 +01:00
|
|
|
def get_and_input_line_combination(self):
|
2017-08-24 00:02:15 +02:00
|
|
|
""" These are the decoder connections of the NAND gates to the A,B,C pins """
|
2018-10-11 18:53:08 +02:00
|
|
|
combination = [["Abar_0", "Abar_1", "Abar_2"],
|
|
|
|
|
["A_0", "Abar_1", "Abar_2"],
|
|
|
|
|
["Abar_0", "A_1", "Abar_2"],
|
|
|
|
|
["A_0", "A_1", "Abar_2"],
|
2020-03-06 22:26:40 +01:00
|
|
|
["Abar_0", "Abar_1", "A_2"],
|
2020-11-03 15:29:17 +01:00
|
|
|
["A_0", "Abar_1", "A_2"],
|
|
|
|
|
["Abar_0", "A_1", "A_2"],
|
2018-10-11 18:53:08 +02:00
|
|
|
["A_0", "A_1", "A_2"]]
|
2020-03-06 22:26:40 +01:00
|
|
|
return combination
|