OpenRAM/compiler/modules/hierarchical_predecode3x8.py

48 lines
2.0 KiB
Python
Raw Normal View History

# See LICENSE for licensing information.
#
2019-06-14 17:43:41 +02:00
# Copyright (c) 2016-2019 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
2016-11-08 18:57:35 +01:00
from hierarchical_predecode import hierarchical_predecode
from globals import OPTS
2016-11-08 18:57:35 +01:00
2016-11-08 18:57:35 +01:00
class hierarchical_predecode3x8(hierarchical_predecode):
"""
Pre 3x8 decoder used in hierarchical_decoder.
"""
2019-01-17 01:15:38 +01:00
def __init__(self, name, height=None):
2020-08-06 20:33:26 +02:00
super().__init__(name, 3, height)
2016-11-08 18:57:35 +01:00
self.create_netlist()
if not OPTS.netlist_only:
self.create_layout()
2016-11-08 18:57:35 +01:00
def create_netlist(self):
self.add_pins()
2018-11-14 01:05:22 +01:00
self.add_modules()
self.create_input_inverters()
connections=[["inbar_0", "inbar_1", "inbar_2", "out_0", "vdd", "gnd"],
2020-11-03 15:29:17 +01:00
["in_0", "inbar_1", "inbar_2", "out_1", "vdd", "gnd"],
["inbar_0", "in_1", "inbar_2", "out_2", "vdd", "gnd"],
2020-11-03 15:29:17 +01:00
["in_0", "in_1", "inbar_2", "out_3", "vdd", "gnd"],
["inbar_0", "inbar_1", "in_2", "out_4", "vdd", "gnd"],
["in_0", "inbar_1", "in_2", "out_5", "vdd", "gnd"],
["inbar_0", "in_1", "in_2", "out_6", "vdd", "gnd"],
["in_0", "in_1", "in_2", "out_7", "vdd", "gnd"]]
self.create_and_array(connections)
2016-11-08 18:57:35 +01:00
def get_and_input_line_combination(self):
""" These are the decoder connections of the NAND gates to the A,B,C pins """
combination = [["Abar_0", "Abar_1", "Abar_2"],
["A_0", "Abar_1", "Abar_2"],
["Abar_0", "A_1", "Abar_2"],
["A_0", "A_1", "Abar_2"],
["Abar_0", "Abar_1", "A_2"],
2020-11-03 15:29:17 +01:00
["A_0", "Abar_1", "A_2"],
["Abar_0", "A_1", "A_2"],
["A_0", "A_1", "A_2"]]
return combination