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OpenRAM/compiler/modules/hierarchical_predecode3x8.py
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# See LICENSE for licensing information.
#
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# Copyright (c) 2016-2024 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
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from openram import OPTS
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from .hierarchical_predecode import hierarchical_predecode
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class hierarchical_predecode3x8(hierarchical_predecode):
"""
Pre 3x8 decoder used in hierarchical_decoder.
"""
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def __init__(self, name, column_decoder=False, height=None):
super().__init__(name, 3, column_decoder, height)
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self.create_netlist()
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if not OPTS.netlist_only:
self.create_layout()
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def create_netlist(self):
self.add_pins()
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self.add_modules()
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self.create_input_inverters()
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connections=[["inbar_0", "inbar_1", "inbar_2", "out_0", "vdd", "gnd"],
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["in_0", "inbar_1", "inbar_2", "out_1", "vdd", "gnd"],
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["inbar_0", "in_1", "inbar_2", "out_2", "vdd", "gnd"],
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["in_0", "in_1", "inbar_2", "out_3", "vdd", "gnd"],
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["inbar_0", "inbar_1", "in_2", "out_4", "vdd", "gnd"],
["in_0", "inbar_1", "in_2", "out_5", "vdd", "gnd"],
["inbar_0", "in_1", "in_2", "out_6", "vdd", "gnd"],
["in_0", "in_1", "in_2", "out_7", "vdd", "gnd"]]
self.create_and_array(connections)
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def get_and_input_line_combination(self):
""" These are the decoder connections of the NAND gates to the A,B,C pins """
combination = [["Abar_0", "Abar_1", "Abar_2"],
["A_0", "Abar_1", "Abar_2"],
["Abar_0", "A_1", "Abar_2"],
["A_0", "A_1", "Abar_2"],
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["Abar_0", "Abar_1", "A_2"],
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["A_0", "Abar_1", "A_2"],
["Abar_0", "A_1", "A_2"],
["A_0", "A_1", "A_2"]]
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return combination