mirror of https://github.com/VLSIDA/OpenRAM.git
107 lines
4.1 KiB
Python
107 lines
4.1 KiB
Python
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import design
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import debug
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import utils
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from tech import GDS,layer,parameter,drc
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class bitcell_1w_1r(design.design):
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"""
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A single bit cell (6T, 8T, etc.) This module implements the
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single memory cell used in the design. It is a hand-made cell, so
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the layout and netlist should be available in the technology
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library.
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"""
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pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"]
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(width,height) = utils.get_libcell_size("cell_1w_1r", GDS["unit"], layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "cell_1w_1r", GDS["unit"])
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def __init__(self, name=""):
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# Ignore the name argument
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design.design.__init__(self, "cell_1w_1r")
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debug.info(2, "Create bitcell with 1W and 1R Port")
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self.width = bitcell_1w_1r.width
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self.height = bitcell_1w_1r.height
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self.pin_map = bitcell_1w_1r.pin_map
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def analytical_delay(self, slew, load=0, swing = 0.5):
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# delay of bit cell is not like a driver(from WL)
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# so the slew used should be 0
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# it should not be slew dependent?
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# because the value is there
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# the delay is only over half transsmission gate
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from tech import spice
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r = spice["min_tx_r"]*3
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c_para = spice["min_tx_drain_c"]
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result = self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew, swing = swing)
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return result
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def list_bitcell_pins(self, col, row):
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""" Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """
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bitcell_pins = ["bl0_{0}".format(col),
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"br0_{0}".format(col),
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"bl1_{0}".format(col),
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"br1_{0}".format(col),
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"wl0_{0}".format(row),
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"wl1_{0}".format(row),
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"vdd",
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"gnd"]
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return bitcell_pins
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def list_all_wl_names(self):
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""" Creates a list of all wordline pin names """
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row_pins = ["wl0", "wl1"]
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return row_pins
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def list_all_bitline_names(self):
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""" Creates a list of all bitline pin names (both bl and br) """
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column_pins = ["bl0", "br0", "bl1", "br1"]
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return column_pins
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def list_all_bl_names(self):
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""" Creates a list of all bl pins names """
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column_pins = ["bl0", "bl1"]
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return column_pins
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def list_all_br_names(self):
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""" Creates a list of all br pins names """
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column_pins = ["br0", "br1"]
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return column_pins
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def list_read_bl_names(self):
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""" Creates a list of bl pin names associated with read ports """
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column_pins = ["bl0", "bl1"]
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return column_pins
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def list_read_br_names(self):
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""" Creates a list of br pin names associated with read ports """
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column_pins = ["br0", "br1"]
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return column_pins
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def list_write_bl_names(self):
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""" Creates a list of bl pin names associated with write ports """
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column_pins = ["bl0"]
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return column_pins
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def list_write_br_names(self):
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""" Creates a list of br pin names asscociated with write ports"""
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column_pins = ["br0"]
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return column_pins
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def analytical_power(self, proc, vdd, temp, load):
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"""Bitcell power in nW. Only characterizes leakage."""
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from tech import spice
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leakage = spice["bitcell_leakage"]
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dynamic = 0 #temporary
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total_power = self.return_power(dynamic, leakage)
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return total_power
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def get_wl_cin(self):
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"""Return the relative capacitance of the access transistor gates"""
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#This is a handmade cell so the value must be entered in the tech.py file or estimated.
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#Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width.
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#FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
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access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
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return 2*access_tx_cin
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