mirror of https://github.com/VLSIDA/OpenRAM.git
23 lines
671 B
Python
23 lines
671 B
Python
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import debug
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import design
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import utils
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from tech import GDS,layer
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class tri_gate(design.design):
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"""
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This module implements the tri gate cell used in the design for
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bit-line isolation. It is a hand-made cell, so the layout and
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netlist should be available in the technology library.
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"""
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pins = ["in", "en", "en_bar", "out", "gnd", "vdd"]
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chars = utils.auto_measure_libcell(pins, "tri_gate", GDS["unit"], layer["boundary"])
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def __init__(self, name):
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design.design.__init__(self, name)
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debug.info(2, "Create tri_gate object")
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self.width = tri_gate.chars["width"]
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self.height = tri_gate.chars["height"]
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