2016-11-08 18:57:35 +01:00
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import debug
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import design
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2016-11-09 21:20:52 +01:00
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from tech import drc
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2016-11-08 18:57:35 +01:00
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from pinv import pinv
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from contact import contact
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from bitcell_array import bitcell_array
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from nor_2 import nor_2
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from ptx import ptx
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from vector import vector
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from globals import OPTS
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class replica_bitline(design.design):
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"""
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Generate a module that simulate the delay of control logic
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and bit line charging.
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Used for memory timing control
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"""
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def __init__(self, name, rows):
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design.design.__init__(self, "replica_bitline")
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g = reload(__import__(OPTS.config.delay_chain))
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self.mod_delay_chain = getattr(g, OPTS.config.delay_chain)
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g = reload(__import__(OPTS.config.replica_bitcell))
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self.mod_replica_bitcell = getattr(g, OPTS.config.replica_bitcell)
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c = reload(__import__(OPTS.config.bitcell))
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self.mod_bitcell = getattr(c, OPTS.config.bitcell)
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self.bitcell_chars = self.mod_bitcell.chars
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for pin in ["en", "out", "vdd", "gnd"]:
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self.add_pin(pin)
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self.rows = rows
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self.create_modules()
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self.cal_modules_offset()
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self.add_modules()
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self.route()
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self.offset_all_coordinates()
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self.DRC_LVS()
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def cal_modules_offset(self):
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pinv_error_offset = 0.025
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# leave some room for metal1 routing
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margin = 3 * drc["minwidth_metal1"]
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# witdth + min_spacing of M1 & M2
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m1rail_space = drc["minwidth_metal1"] + drc["metal1_to_metal1"]
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m2rail_space = drc["minwidth_metal2"] + drc["metal2_to_metal2"]
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# leave some margin as bit cell layout exceeds its own orgin
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route_margin = 8 * m2rail_space
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well_margin = 2 * drc["pwell_enclose_nwell"]
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bitcell_array_spacing = max(route_margin, well_margin)
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# now extra space for BL and WL of RBC
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gnd_route_margin = 5 * m2rail_space
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y_off = (self.inv.height * 2 + pinv_error_offset
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+ max(drc["pwell_enclose_nwell"],
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m1rail_space * 4))
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self.delay_chain_offset = vector(self.delay_chain.height,y_off)
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self.en_input_offset = vector(0, y_off - m2rail_space)
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self.en_nor_offset = vector(self.nor.width + margin,
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self.inv.height * 2)
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self.BL_inv_offset = vector(self.en_nor_offset.x - self.inv.width, 0)
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self.access_tx_offset = vector(self.en_nor_offset.x - self.nor.width
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+ self.access_tx.height + margin,
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self.inv.height * 0.5)
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self.replica_bitline_offset = vector(self.delay_chain_offset.x
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+ bitcell_array_spacing,
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self.bitcell_chars["height"] + gnd_route_margin)
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self.delay_inv_offset = vector(self.delay_chain_offset.x - self.inv.width,
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self.inv.height * 2)
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self.height = m1rail_space + max(self.delay_chain_offset.y + self.inv.height,
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self.replica_bitline_offset.y
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+ self.bitline_load.height
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+ 0.5 * self.bitcell_chars["height"])
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self.width = (self.replica_bitline_offset.x + self.replica_bitcell.width)
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def create_modules(self):
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""" create module """
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self.replica_bitcell = self.mod_replica_bitcell()
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self.add_mod(self.replica_bitcell)
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# This is the replica bitline load column that is the same height as our array
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self.bitline_load = bitcell_array(name="bitline_load",
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cols=1,
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rows=self.rows)
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self.add_mod(self.bitline_load)
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# FIXME: This just creates 3 1x inverters
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self.delay_chain = self.mod_delay_chain("delay_chain",
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[1, 1, 1])
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self.add_mod(self.delay_chain)
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self.inv = pinv(name="RBL_inv",
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nmos_width=drc["minwidth_tx"])
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self.add_mod(self.inv)
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# These aren't for instantiating, but we use them to get the dimensions
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self.poly_contact = contact(layer_stack=("poly", "contact", "metal1"))
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self.m1m2_via = contact(layer_stack=("metal1", "via1", "metal2"))
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self.m2m3_via = contact(layer_stack=("metal2", "via2", "metal3"))
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self.nor = nor_2(name="replica_bitline_nor2",
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nmos_width=drc["minwidth_tx"])
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self.add_mod(self.nor)
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self.access_tx = ptx(name="access_tx",
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width=drc["minwidth_tx"],
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mults=1,
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tx_type="pmos")
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self.add_mod(self.access_tx)
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def add_modules(self):
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"""add mod instance in layout """
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self.add_inst(name="BL_inv",
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mod=self.inv,
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offset=self.BL_inv_offset)
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self.connect_inst(["bl[0]", "out", "vdd", "gnd"])
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self.add_inst(name="BL_access_tx",
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mod=self.access_tx,
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offset=self.access_tx_offset,
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rotate=90)
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# D, G, S, B
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self.connect_inst(["vdd", "delayed_en", "bl[0]", "vdd"])
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self.add_inst(name="delay_chain",
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mod=self.delay_chain,
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offset=self.delay_chain_offset,
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rotate=90)
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self.connect_inst(["en", "delayed_en", "vdd", "gnd"])
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self.add_inst(name="bitcell",
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mod=self.replica_bitcell,
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offset=self.replica_bitline_offset,
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mirror="MX")
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self.connect_inst(["bl[0]", "br[0]", "delayed_en", "vdd", "gnd"])
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self.add_loads()
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self.expan_the_well_to_BL_inv()
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def expan_the_well_to_BL_inv(self):
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width = self.BL_inv_offset.x - self.access_tx_offset.x + self.inv.width
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well_offset = self.access_tx_offset - vector(self.access_tx.width, 0)
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for layer in ["nwell", "vtg"]:
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self.add_rect(layer=layer,
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offset=well_offset,
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width=width,
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height= 2*self.access_tx.width)
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def add_loads(self):
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self.add_inst(name="load",
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mod=self.bitline_load,
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offset=self.replica_bitline_offset)
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temp = []
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for i in range(1):
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temp.append("bl[{0}]".format(i))
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temp.append("br[{0}]".format(i))
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for j in range(self.rows):
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temp.append("gnd".format(j))
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temp = temp + ["vdd", "gnd"]
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self.connect_inst(temp)
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def route(self):
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"""connect modules together"""
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# calculate pin offset
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correct = vector(0, 0.5 * drc["minwidth_metal1"])
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self.out_offset = self.BL_inv_offset + self.inv.Z_position + correct
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=self.out_offset)
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m1_pin_offset = self.out_offset - correct
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self.add_rect(layer="metal1",
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offset=m1_pin_offset,
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width=self.m1m2_via.width,
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height=self.m1m2_via.height)
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self.add_rect(layer="metal2",
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offset=m1_pin_offset,
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width=self.m2m3_via.width,
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height=self.m2m3_via.height)
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BL_inv_in = self.BL_inv_offset + self.inv.A_position + correct
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BL_offset = self.replica_bitline_offset + vector(1,0).scale(self.bitcell_chars["BL"])
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pin_offset = self.delay_chain.clk_out_offset.rotate().scale(-1,1)
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delay_chain_output = self.delay_chain_offset + pin_offset
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self.create_input()
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self.route_BL_t_BL_inv(BL_offset, BL_inv_in)
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self.route_access_tx(delay_chain_output, BL_inv_in)
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self.route_vdd()
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self.route_gnd()
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# route loads after gnd and vdd created
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self.route_loads()
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self.route_RC()
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def create_input(self):
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# create routing module based on module offset
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correct = vector(0.5 * drc["minwidth_metal1"], 0)
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pin_offset = self.delay_chain.clk_in_offset.rotate().scale(-1,1)
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input_offset = self.delay_chain_offset + pin_offset + correct
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mid1 = [input_offset[0], self.en_input_offset[1]]
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self.add_path("metal1", [self.en_input_offset, mid1, input_offset])
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self.add_label(text="en",
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layer="metal1",
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offset=self.en_input_offset)
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def route_nor2A_t_dc(self, nor_A, delayed_en_offset):
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# delay chain output to m2
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dc_offset = [delayed_en_offset[0], delayed_en_offset[1]]
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mid1 = [dc_offset[0], self.en_nor_offset
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[1] + 3 * drc["minwidth_metal2"]]
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mid2 = [self.delay_chain_offset[0] + 3*drc["minwidth_metal2"],
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dc_offset[1]]
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mid3 = [mid2[0], nor_A[1]]
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self.add_wire(("metal2", "via1", "metal1"),
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[dc_offset, mid2, mid3, nor_A])
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def route_nor2B_t_BL_inv(self, nor_B, BL_inv_out):
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mid1 = [nor_B[0] + 0.5 * drc["metal2_to_metal2"], nor_B[1]]
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self.add_wire(("metal2", "via1", "metal1"),
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[nor_B, mid1, BL_inv_out])
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def route_BL_t_BL_inv(self, BL_offset, BL_inv_in):
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# BL_inv input to M3
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mid1 = [BL_inv_in[0],
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BL_inv_in[1] - drc["metal2_to_metal2"] - self.m1m2_via.width]
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mid2 = [self.en_nor_offset[0] + 3*drc["metal1_to_metal1"],
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mid1[1]]
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mid3 = [mid2[0],
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self.replica_bitline_offset[1] - self.replica_bitcell.height
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- 0.5 * (self.m1m2_via.height + drc["metal1_to_metal1"])
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- 2 * drc["metal1_to_metal1"]]
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self.add_wire(("metal1", "via1", "metal2"),
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[BL_inv_in, mid1, mid2, mid3])
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# need to fix the mid point as this is done with two wire
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# this seems to cover the metal1 error of the wire
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offset = mid3 - vector( [0.5 * drc["minwidth_metal1"]] * 2)
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self.add_rect(layer="metal1",
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offset=offset,
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width=drc["minwidth_metal1"],
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height=drc["minwidth_metal1"])
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mid4 = [BL_offset[0], mid3[1]]
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self.add_wire(("metal2", "via1", "metal1"),
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[BL_offset, mid4, mid3])
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def route_access_tx(self, delay_chain_output, BL_inv_in):
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self.route_tx_gate(delay_chain_output)
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self.route_tx_drain()
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self.route_tx_source(BL_inv_in)
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def route_tx_gate(self, delay_chain_output):
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# gate input for access tx
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offset = (self.access_tx.poly_positions[0].rotate().scale(0,1)
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+ self.access_tx_offset)
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width = -6 * drc["minwidth_metal1"]
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self.add_rect(layer="poly",
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offset=offset,
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width=width,
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height=drc["minwidth_poly"])
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y_off = 0.5 * (drc["minwidth_poly"] - self.poly_contact.height)
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offset = offset + vector(width, y_off)
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self.add_contact(layers=("poly", "contact", "metal1"),
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offset=offset)
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# route gate to delay_chain output
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gate_offset = offset + vector(0.5 * drc["minwidth_metal1"],
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0.5 * self.poly_contact.width)
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self.route_access_tx_t_delay_chain(gate_offset, delay_chain_output)
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self.route_access_tx_t_WL(gate_offset)
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def route_access_tx_t_delay_chain(self, offset, delay_chain_output):
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m2rail_space = (drc["minwidth_metal2"] + drc["metal2_to_metal2"])
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mid1 = [offset[0], self.delay_chain_offset[1] - 3 * m2rail_space]
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mid2 = [delay_chain_output[0], mid1[1]]
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# Note the inverted wire stack
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self.add_wire(("metal2", "via1", "metal1"),
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[offset, mid1, mid2, delay_chain_output])
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=delay_chain_output,
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mirror="MX")
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def route_access_tx_t_WL(self, offset):
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m1m2_via_offset = offset - vector(0.5 * self.m1m2_via.width,
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0.5 * self.m1m2_via.height)
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=m1m2_via_offset)
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# route gate to RC WL
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RC_WL = self.replica_bitline_offset - vector(0,1).scale(self.bitcell_chars["WL"])
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mid1 = [offset[0], 0]
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mid2 = [self.en_nor_offset[0] + 3 * drc["metal1_to_metal1"],
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mid1[1]]
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mid3 = [RC_WL[0] - drc["minwidth_metal1"] - self.m1m2_via.height,
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mid1[1]]
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mid4 = [mid3[0], RC_WL[1]]
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self.add_path("metal2", [offset, mid1, mid2, mid3, mid4])
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offset = mid4 - vector([0.5 * drc["minwidth_metal1"]]*2)
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width = RC_WL[0] - offset[0]
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# enter the bit line array with metal1
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via_offset = [mid4[0] - 0.5 * self.m1m2_via.width,
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offset[1] - 0.5 * (self.m1m2_via.height
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- drc["minwidth_metal1"])]
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=via_offset)
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self.add_rect(layer="metal1",
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offset=offset,
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width=width,
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height=drc["minwidth_metal1"])
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def route_tx_drain(self):
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# route drain to Vdd
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active_offset = self.access_tx.active_contact_positions[1].rotate().scale(-1,1)
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correct = vector(drc["minwidth_metal1"],
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self.access_tx.active_contact.width).scale(-0.5, 0.5)
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drain_offset = self.access_tx_offset + active_offset + correct
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vdd_rail = [self.delay_chain_offset[0] + 9 * drc["minwidth_metal2"],
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self.height]
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close_Vdd_offset = self.BL_inv_offset + vector(0, self.inv.height)
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self.add_path("metal1", [drain_offset, close_Vdd_offset])
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mid = [vdd_rail[0], close_Vdd_offset[1]]
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self.add_wire(("metal2", "via1", "metal1"),
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[close_Vdd_offset, mid, vdd_rail])
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def route_tx_source(self, BL_inv_in):
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# route source to BL inv input which is connected to BL
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active_offset = self.access_tx.active_contact_positions[0].rotate().scale(-1,1)
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correct = vector(drc["minwidth_metal1"],
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self.access_tx.active_contact.width).scale(-0.5, 0.5)
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source_offset = self.access_tx_offset + active_offset + correct
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self.add_path("metal1", [source_offset, BL_inv_in])
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def route_vdd(self):
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vdd_offset = vector(0, self.height)
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_offset,
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width=self.width,
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height=drc["minwidth_metal1"])
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# delay chain vdd to vertical vdd rail and
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start = self.delay_chain_offset - vector(0.5 * self.delay_chain.height, 0)
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m1rail_space = (drc["minwidth_metal1"] + drc["metal1_to_metal1"])
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mid1 = start - vector(0, m1rail_space)
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mid2 = [self.delay_chain_offset[0] + 9 * drc["minwidth_metal2"],
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mid1[1]]
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end = [mid2[0], vdd_offset[1]]
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self.add_path(("metal1"), [start, mid1, mid2])
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self.add_wire(("metal2", "via1", "metal1"), [mid1, mid2, end])
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def route_gnd(self):
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"""route gnd of delay chain, en_nor, en_inv and BL_inv"""
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# route delay chain gnd to BL_inv gnd
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# gnd Node between BL_inv access tx and delay chain, and is below
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# en_input
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self.gnd_position = self.delay_chain_offset
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BL_gnd_offset = self.BL_inv_offset
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mid1 = vector(0, self.BL_inv_offset.y)
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rail2_space = drc["minwidth_metal2"] + drc["metal2_to_metal2"]
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y_off = self.gnd_position.y + self.delay_chain.width + rail2_space
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mid2 = vector(mid1.x, y_off)
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share_gnd = vector(self.gnd_position.x, mid2.y)
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# Note the inverted stacks
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self.add_wire(("metal2", "via1", "metal1"),
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[BL_gnd_offset, mid1, mid2, share_gnd, self.gnd_position])
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self.add_label(text="gnd",
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layer="metal1",
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offset=self.gnd_position)
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# connect to the metal1 gnd of delay chain
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offset = mid2 - vector(0.5 * drc["minwidth_metal1"], 0)
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self.add_rect(layer="metal1",
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offset=offset,
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width=drc["minwidth_metal1"],
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height=-self.delay_chain.width)
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offset = [offset[0] + self.delay_chain.height,
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mid2[1]]
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self.add_rect(layer="metal1",
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offset=offset,
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width=drc["minwidth_metal1"],
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height=-self.delay_chain.width)
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def route_loads(self):
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"""connect all the loads word line to gnd"""
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vdd_offset = [self.delay_chain_offset[0] + 9*drc["minwidth_metal2"],
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self.height]
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=vdd_offset,
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mirror="MX")
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gnd_offset = (self.delay_chain_offset
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+ vector([drc["minwidth_metal1"]]*2).scale(-.5,.5))
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for i in range(self.rows):
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WL_offset = (self.replica_bitline_offset
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+ self.bitline_load.WL_positions[i].scale(0,1))
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mid = [self.delay_chain_offset[0] + 6 * drc["minwidth_metal2"],
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gnd_offset[1]]
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self.add_wire(("metal2", "via1", "metal1"), [gnd_offset, mid, WL_offset])
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if i % 2 == 0:
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load_vdd_offset = (self.replica_bitline_offset
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+ self.bitline_load.vdd_positions[i])
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mid = [vdd_offset[0], load_vdd_offset[1]]
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self.add_wire(("metal2", "via1", "metal1"), [vdd_offset, mid, load_vdd_offset])
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def route_RC(self):
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"""route vdd gnd to the replica cell """
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# connect vdd
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RC_vdd = self.replica_bitline_offset + vector(1,-1).scale(self.bitcell_chars["vdd"])
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vdd_offset = [self.delay_chain_offset[0] + 9 * drc["minwidth_metal2"],
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self.height]
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mid = [vdd_offset[0], RC_vdd[1]]
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# Note the inverted stacks
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self.add_wire(("metal2", "via1", "metal1"), [vdd_offset, mid, RC_vdd])
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gnd_offset = self.BL_inv_offset - vector(self.inv.width, 0)
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load_gnd = (self.replica_bitline_offset
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+ vector(self.bitcell_chars["gnd"][0], self.bitline_load.height))
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mid = [load_gnd[0], gnd_offset[1]]
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self.add_wire(("metal2", "via1", "metal1"), [gnd_offset, mid, load_gnd])
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load_gnd = (self.replica_bitline_offset
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+ vector(0, self.bitline_load.height))
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mid = [load_gnd[0], gnd_offset[1]]
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self.add_wire(("metal2", "via1", "metal1"), [gnd_offset, mid, load_gnd])
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