mirror of https://github.com/VLSIDA/OpenRAM.git
23 lines
718 B
Python
23 lines
718 B
Python
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import design
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import debug
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import utils
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from tech import GDS,layer
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class replica_bitcell(design.design):
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"""
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A single bit cell (6T, 8T, etc.)
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This module implements the single memory cell used in the design. It
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is a hand-made cell, so the layout and netlist should be available in
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the technology library. """
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pins = ["BL", "BR", "WL", "vdd", "gnd"]
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chars = utils.auto_measure_libcell(pins, "replica_cell_6t", GDS["unit"], layer["boundary"])
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def __init__(self, name="replica_cell_6t"):
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design.design.__init__(self, name)
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debug.info(2, "Create bitcell object")
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self.width = replica_bitcell.chars["width"]
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self.height = replica_bitcell.chars["height"]
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