mirror of https://github.com/VLSIDA/OpenRAM.git
49 lines
1.8 KiB
Python
49 lines
1.8 KiB
Python
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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import debug
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import utils
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from tech import GDS,layer,parameter,drc
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import logical_effort
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class dummy_bitcell(design.design):
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"""
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A single bit cell (6T, 8T, etc.) This module implements the
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single memory cell used in the design. It is a hand-made cell, so
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the layout and netlist should be available in the technology
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library.
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"""
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pin_names = ["bl", "br", "wl", "vdd", "gnd"]
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(width,height) = utils.get_libcell_size("dummy_cell_6t", GDS["unit"], layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "dummy_cell_6t", GDS["unit"])
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def __init__(self, name=""):
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# Ignore the name argument
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design.design.__init__(self, "dummy_cell_6t")
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debug.info(2, "Create dummy bitcell")
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self.width = dummy_bitcell.width
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self.height = dummy_bitcell.height
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self.pin_map = dummy_bitcell.pin_map
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def analytical_power(self, corner, load):
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"""Bitcell power in nW. Only characterizes leakage."""
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from tech import spice
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leakage = spice["bitcell_leakage"]
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dynamic = 0 #temporary
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total_power = self.return_power(dynamic, leakage)
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return total_power
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def get_wl_cin(self):
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"""Return the relative capacitance of the access transistor gates"""
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#This is a handmade cell so the value must be entered in the tech.py file or estimated.
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#Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width.
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access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
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return 2*access_tx_cin
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