OpenRAM/compiler/router/tests/config_freepdk45.py

mirror of https://github.com/VLSIDA/OpenRAM.git
word_size = 1
num_words = 16

tech_name = "freepdk45"
process_corners = ["TT"]
supply_voltages = [1.0]
temperatures = [25]
Add router data structure, blockage parser, pin parser, initial unit tests 2016-11-17 00:02:07 +01:00			`word_size = 1`
			`num_words = 16`

			`tech_name = "freepdk45"`
Clean up GdsMill. Fix rotate bug I introduced in transFlags! 2018-08-30 00:32:45 +02:00			`process_corners = ["TT"]`
			`supply_voltages = [1.0]`
			`temperatures = [25]`

Add router data structure, blockage parser, pin parser, initial unit tests 2016-11-17 00:02:07 +01:00