OpenRAM/compiler/tests/config_20_scn3me_subm.py

mirror of https://github.com/VLSIDA/OpenRAM.git
word_size = 1
num_words = 16
num_banks = 1

tech_name = "scn3me_subm"
process_corners = ["TT"]
supply_voltages = [5.0]
temperatures = [25]
RELEASE 1.0 2016-11-08 18:57:35 +01:00			`word_size = 1`
			`num_words = 16`
			`num_banks = 1`

			`tech_name = "scn3me_subm"`
Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken. 2018-02-12 18:33:23 +01:00			`process_corners = ["TT"]`
			`supply_voltages = [5.0]`
			`temperatures = [25]`
RELEASE 1.0 2016-11-08 18:57:35 +01:00