2016-11-08 18:57:35 +01:00
|
|
|
from math import log
|
|
|
|
|
import design
|
|
|
|
|
from tech import drc
|
|
|
|
|
import debug
|
|
|
|
|
from vector import vector
|
|
|
|
|
from globals import OPTS
|
|
|
|
|
|
|
|
|
|
class write_driver_array(design.design):
|
|
|
|
|
"""
|
|
|
|
|
Array of tristate drivers to write to the bitlines through the column mux.
|
|
|
|
|
Dynamically generated write driver array of all bitlines.
|
|
|
|
|
"""
|
|
|
|
|
|
|
|
|
|
def __init__(self, columns, word_size):
|
|
|
|
|
design.design.__init__(self, "write_driver_array")
|
|
|
|
|
debug.info(1, "Creating {0}".format(self.name))
|
|
|
|
|
|
|
|
|
|
self.columns = columns
|
|
|
|
|
self.word_size = word_size
|
2018-05-12 01:32:00 +02:00
|
|
|
self.words_per_row = int(columns / word_size)
|
2016-11-08 18:57:35 +01:00
|
|
|
|
2018-08-28 19:24:09 +02:00
|
|
|
self.create_netlist()
|
|
|
|
|
if not OPTS.netlist_only:
|
|
|
|
|
self.create_layout()
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
def create_netlist(self):
|
|
|
|
|
self.add_modules()
|
|
|
|
|
self.add_pins()
|
|
|
|
|
self.create_write_array()
|
|
|
|
|
|
|
|
|
|
def create_layout(self):
|
2018-09-01 08:28:06 +02:00
|
|
|
|
|
|
|
|
if self.bitcell.width > self.driver.width:
|
|
|
|
|
self.width = self.columns * self.bitcell.width
|
|
|
|
|
else:
|
|
|
|
|
self.width = self.columns * self.driver.width
|
|
|
|
|
|
2018-08-28 19:24:09 +02:00
|
|
|
self.height = self.driver.height
|
2017-08-24 00:02:15 +02:00
|
|
|
|
2018-08-28 19:24:09 +02:00
|
|
|
self.place_write_array()
|
|
|
|
|
self.add_layout_pins()
|
|
|
|
|
self.DRC_LVS()
|
2016-11-08 18:57:35 +01:00
|
|
|
|
|
|
|
|
def add_pins(self):
|
2017-08-25 01:22:14 +02:00
|
|
|
for i in range(self.word_size):
|
|
|
|
|
self.add_pin("data[{0}]".format(i))
|
|
|
|
|
for i in range(self.word_size):
|
2017-12-19 18:01:24 +01:00
|
|
|
self.add_pin("bl[{0}]".format(i))
|
|
|
|
|
self.add_pin("br[{0}]".format(i))
|
2017-09-11 23:30:52 +02:00
|
|
|
self.add_pin("en")
|
2016-11-08 18:57:35 +01:00
|
|
|
self.add_pin("vdd")
|
|
|
|
|
self.add_pin("gnd")
|
|
|
|
|
|
2018-08-28 19:24:09 +02:00
|
|
|
def add_modules(self):
|
|
|
|
|
from importlib import reload
|
|
|
|
|
c = reload(__import__(OPTS.write_driver))
|
|
|
|
|
self.mod_write_driver = getattr(c, OPTS.write_driver)
|
|
|
|
|
self.driver = self.mod_write_driver("write_driver")
|
|
|
|
|
self.add_mod(self.driver)
|
2018-09-01 08:28:06 +02:00
|
|
|
|
|
|
|
|
c = reload(__import__(OPTS.bitcell))
|
|
|
|
|
self.mod_bitcell = getattr(c, OPTS.bitcell)
|
|
|
|
|
self.bitcell = self.mod_bitcell()
|
|
|
|
|
self.add_mod(self.bitcell)
|
2016-11-08 18:57:35 +01:00
|
|
|
|
|
|
|
|
def create_write_array(self):
|
2017-08-25 01:22:14 +02:00
|
|
|
self.driver_insts = {}
|
2017-08-24 00:02:15 +02:00
|
|
|
for i in range(0,self.columns,self.words_per_row):
|
|
|
|
|
name = "Xwrite_driver{}".format(i)
|
2018-05-12 01:32:00 +02:00
|
|
|
index = int(i/self.words_per_row)
|
|
|
|
|
self.driver_insts[index]=self.add_inst(name=name,
|
2018-08-27 20:13:34 +02:00
|
|
|
mod=self.driver)
|
2017-09-11 23:30:52 +02:00
|
|
|
|
2018-05-12 01:32:00 +02:00
|
|
|
self.connect_inst(["data[{0}]".format(index),
|
|
|
|
|
"bl[{0}]".format(index),
|
|
|
|
|
"br[{0}]".format(index),
|
2017-09-11 23:30:52 +02:00
|
|
|
"en", "vdd", "gnd"])
|
2016-11-08 18:57:35 +01:00
|
|
|
|
|
|
|
|
|
2018-08-27 20:13:34 +02:00
|
|
|
def place_write_array(self):
|
2018-09-01 08:28:06 +02:00
|
|
|
if self.bitcell.width > self.driver.width:
|
|
|
|
|
driver_spacing = self.bitcell.width
|
|
|
|
|
else:
|
|
|
|
|
driver_spacing = self.driver.width
|
|
|
|
|
|
2018-08-27 20:13:34 +02:00
|
|
|
for i in range(0,self.columns,self.words_per_row):
|
2018-08-28 02:25:39 +02:00
|
|
|
index = int(i/self.words_per_row)
|
2018-09-01 08:28:06 +02:00
|
|
|
base = vector(i * driver_spacing,0)
|
2018-08-28 02:25:39 +02:00
|
|
|
self.driver_insts[index].place(base)
|
2018-08-27 20:13:34 +02:00
|
|
|
|
|
|
|
|
|
2017-08-24 00:02:15 +02:00
|
|
|
def add_layout_pins(self):
|
2017-08-25 01:22:14 +02:00
|
|
|
for i in range(self.word_size):
|
|
|
|
|
din_pin = self.driver_insts[i].get_pin("din")
|
|
|
|
|
self.add_layout_pin(text="data[{0}]".format(i),
|
2017-08-24 00:02:15 +02:00
|
|
|
layer="metal2",
|
2017-08-25 01:22:14 +02:00
|
|
|
offset=din_pin.ll(),
|
|
|
|
|
width=din_pin.width(),
|
2017-08-24 00:02:15 +02:00
|
|
|
height=din_pin.height())
|
2018-02-01 02:37:16 +01:00
|
|
|
bl_pin = self.driver_insts[i].get_pin("bl")
|
2017-08-25 01:22:14 +02:00
|
|
|
self.add_layout_pin(text="bl[{0}]".format(i),
|
2017-08-24 00:02:15 +02:00
|
|
|
layer="metal2",
|
2017-08-25 01:22:14 +02:00
|
|
|
offset=bl_pin.ll(),
|
|
|
|
|
width=bl_pin.width(),
|
2017-08-24 00:02:15 +02:00
|
|
|
height=bl_pin.height())
|
|
|
|
|
|
2018-02-01 02:37:16 +01:00
|
|
|
br_pin = self.driver_insts[i].get_pin("br")
|
2017-08-25 01:22:14 +02:00
|
|
|
self.add_layout_pin(text="br[{0}]".format(i),
|
2017-08-24 00:02:15 +02:00
|
|
|
layer="metal2",
|
2017-08-25 01:22:14 +02:00
|
|
|
offset=br_pin.ll(),
|
|
|
|
|
width=br_pin.width(),
|
2017-08-24 00:02:15 +02:00
|
|
|
height=br_pin.height())
|
2018-04-11 18:29:54 +02:00
|
|
|
|
|
|
|
|
for n in ["vdd", "gnd"]:
|
2018-04-17 01:15:35 +02:00
|
|
|
pin_list = self.driver_insts[i].get_pins(n)
|
|
|
|
|
for pin in pin_list:
|
|
|
|
|
pin_pos = pin.center()
|
|
|
|
|
# Add the M2->M3 stack
|
|
|
|
|
self.add_via_center(layers=("metal2", "via2", "metal3"),
|
|
|
|
|
offset=pin_pos)
|
|
|
|
|
self.add_layout_pin_rect_center(text=n,
|
|
|
|
|
layer="metal3",
|
|
|
|
|
offset=pin_pos)
|
2018-04-11 18:29:54 +02:00
|
|
|
|
|
|
|
|
|
2016-11-08 18:57:35 +01:00
|
|
|
|
2017-09-11 23:30:52 +02:00
|
|
|
self.add_layout_pin(text="en",
|
2017-08-24 00:02:15 +02:00
|
|
|
layer="metal1",
|
2017-08-25 01:22:14 +02:00
|
|
|
offset=self.driver_insts[0].get_pin("en").ll().scale(0,1),
|
|
|
|
|
width=self.width,
|
2017-08-24 00:02:15 +02:00
|
|
|
height=drc['minwidth_metal1'])
|
|
|
|
|
|
|
|
|
|
|
2016-11-08 18:57:35 +01:00
|
|
|
|