luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
OpenRAM/technology/scn4m_subm/sp_lib/dummy_cell_1rw.sp

18 lines
408 B
SourcePawn
Raw Normal View History

Add replica row with dummy cells.
2019-06-14 23:38:55 +02:00
Rework bitcells. Name them 1port and 2port consistently. Allow cell overrides to cell_1rw and cell_2rw or other. Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
2020-11-13 19:07:40 +01:00
*********************** "dummy_cell_1rw" ******************************
.SUBCKT dummy_cell_1rw bl br wl vdd gnd
Add replica row with dummy cells.
2019-06-14 23:38:55 +02:00
* Inverter 1
fix custom bitcell labeling; fix gds scaling in labeling
2020-01-15 10:00:02 +01:00
M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u
M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u
Add replica row with dummy cells.
2019-06-14 23:38:55 +02:00
* Inverter 2
fix custom bitcell labeling; fix gds scaling in labeling
2020-01-15 10:00:02 +01:00
M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u
M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u
Add replica row with dummy cells.
2019-06-14 23:38:55 +02:00
* Access transistors
M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u
fix custom bitcell labeling; fix gds scaling in labeling
2020-01-15 10:00:02 +01:00
M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u
Add replica row with dummy cells.
2019-06-14 23:38:55 +02:00
.ENDS