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PhillipRambo 5b7b21b897 create media folder 2025-07-25 17:01:52 +02:00
PhillipRambo 90eb17a061
Add files via upload 2025-07-25 17:00:36 +02:00
PhillipRambo 18b21b1d4d push pex example 2025-07-25 16:33:53 +02:00
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66 changed files with 21623 additions and 905 deletions
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4
modules/module_0_foundations/sg13_nmos_lv.py
View File

@ -43,8 +43,8 @@ ngspice = NgspiceSimulator(
nmos_sweep = TransistorSweep(
mos_type="nmos",
vgs=(0, 1.2, 0.01),
vds=(0, 1.2, 0.01),
vgs=(0, 1.2, 0.1),
vds=(0, 1.2, 0.1),
vbs=(0, -1.2, -0.1),
length = [130e-9, 260e-9, 390e-9, 520e-9, 650e-9, 780e-9, 910e-9, 1040e-9, 1170e-9, 1300e-9, 1430e-9, 1560e-9, 1690e-9, 1820e-9, 1950e-9, 2080e-9, 2210e-9, 2340e-9, 2470e-9, 2600e-9, 2730e-9, 2860e-9, 2990e-9, 3120e-9, 3250e-9, 3380e-9, 3510e-9, 3640e-9, 3770e-9, 3900e-9, 4030e-9, 4160e-9, 4290e-9, 4420e-9, 4550e-9, 4680e-9, 4810e-9, 4940e-9, 5070e-9, 5200e-9, 5330e-9, 5460e-9, 5590e-9, 5720e-9, 5850e-9, 5980e-9, 6110e-9, 6240e-9, 6370e-9, 6500e-9, 6630e-9, 6760e-9, 6890e-9, 7020e-9, 7150e-9, 7280e-9, 7410e-9, 7540e-9, 7670e-9, 7800e-9, 7930e-9, 8060e-9, 8190e-9, 8320e-9, 8450e-9, 8580e-9, 8710e-9, 8840e-9, 8970e-9, 9100e-9, 9230e-9, 9360e-9, 9490e-9, 9620e-9, 9750e-9, 9880e-9]
)

4
modules/module_1_bandgap_reference/part_1_OTA/testbenches/ota_testbench_mc_mis.sch
View File

@ -70,12 +70,12 @@ C {devices/code_shown.sym} 25 -1260 0 0 {name=NGSPICE only_toplevel=false
value="
.control
let run = 1
let mc_runs = 100
let mc_runs = 10
set curplot = new
set scratch = $curplot
dowhile run <= mc_runs
reset
dc temp 0 70 5
dc temp 70 0 5
set run = $&run
set dc = $curplot
setplot $scratch

508
modules/module_1_bandgap_reference/part_3_layout/BGR_layout/final_bandgapreference/sg13g2_minimal.lyrdb Normal file
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@ -0,0 +1,508 @@
<?xml version="1.0" encoding="utf-8"?>
<report-database>
<description>design rules: sg13g2_minimal | layout cell: full_bandgap</description>
<original-file>full_bandgap_layout_pads.gds</original-file>
<generator>drc: script='/home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_minimal.lydrc'</generator>
<top-cell>full_bandgap</top-cell>
<tags>
<tag>
<name>waived</name>
<description/>
</tag>
<tag>
<name>red</name>
<description/>
</tag>
<tag>
<name>green</name>
<description/>
</tag>
<tag>
<name>blue</name>
<description/>
</tag>
<tag>
<name>yellow</name>
<description/>
</tag>
<tag>
<name>important</name>
<description/>
</tag>
</tags>
<categories>
<category>
<name>Act.a</name>
<description>Min. Activ width = 0.15</description>
<categories>
</categories>
</category>
<category>
<name>Act.b</name>
<description>Min. Activ space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>AFil.g/g1</name>
<description>Global Activ density [%] = 35.00 .. 55.00</description>
<categories>
</categories>
</category>
<category>
<name>AFil.g2/g3</name>
<description>Activ coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 65.00</description>
<categories>
</categories>
</category>
<category>
<name>TGO.f</name>
<description>Min. ThickGateOx width = 0.86</description>
<categories>
</categories>
</category>
<category>
<name>Gat.a</name>
<description>Min. GatPoly width = 0.13</description>
<categories>
</categories>
</category>
<category>
<name>Gat.b</name>
<description>Min. GatPoly space or notch = 0.18</description>
<categories>
</categories>
</category>
<category>
<name>Gat.d</name>
<description>Min. GatPoly space to Activ = 0.07</description>
<categories>
</categories>
</category>
<category>
<name>GFil.g</name>
<description>Min. global GatPoly density [%] = 15.00</description>
<categories>
</categories>
</category>
<category>
<name>Cnt.a</name>
<description>Min. and max. Cont width = 0.16</description>
<categories>
</categories>
</category>
<category>
<name>Cnt.b</name>
<description>Min. Cont space = 0.18</description>
<categories>
</categories>
</category>
<category>
<name>M1.a</name>
<description>Min. Metal1 width = 0.16</description>
<categories>
</categories>
</category>
<category>
<name>M1.b</name>
<description>Min. Metal1 space or notch = 0.18</description>
<categories>
</categories>
</category>
<category>
<name>M1.j/k</name>
<description>Global Metal1 density [%] = 35.0 .. 60.0</description>
<categories>
</categories>
</category>
<category>
<name>M2.a</name>
<description>Min. Metal2 width = 0.20</description>
<categories>
</categories>
</category>
<category>
<name>M2.b</name>
<description>Min. Metal2 space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>M2.j/k</name>
<description>Global Metal2 density [%] = 35.00 .. 60.00</description>
<categories>
</categories>
</category>
<category>
<name>M3.a</name>
<description>Min. Metal3 width = 0.20</description>
<categories>
</categories>
</category>
<category>
<name>M3.b</name>
<description>Min. Metal3 space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>M3.j/k</name>
<description>Global Metal3 density [%] = 35.00 .. 60.00</description>
<categories>
</categories>
</category>
<category>
<name>M4.a</name>
<description>Min. Metal4 width = 0.20</description>
<categories>
</categories>
</category>
<category>
<name>M4.b</name>
<description>Min. Metal4 space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>M4.j/k</name>
<description>Global Metal4 density [%] = 35.00 .. 60.00</description>
<categories>
</categories>
</category>
<category>
<name>M5.a</name>
<description>Min. Metal5 width = 0.20</description>
<categories>
</categories>
</category>
<category>
<name>M5.b</name>
<description>Min. Metal5 space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>M5.j/k</name>
<description>Global Metal5 density [%] = 35.00 .. 60.00</description>
<categories>
</categories>
</category>
<category>
<name>M1Fil.h/k</name>
<description>Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>M2Fil.h/k</name>
<description>Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>M3Fil.h/k</name>
<description>Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>M4Fil.h/k</name>
<description>Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>M5Fil.h/k</name>
<description>Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>V1.a</name>
<description>Min. and max. Via1 width = 0.19</description>
<categories>
</categories>
</category>
<category>
<name>V1.b</name>
<description>Min. Via1 space = 0.22</description>
<categories>
</categories>
</category>
<category>
<name>V2.a</name>
<description>Min. and max. Via2 width = 0.19</description>
<categories>
</categories>
</category>
<category>
<name>V2.b</name>
<description>Min. Via2 space = 0.22</description>
<categories>
</categories>
</category>
<category>
<name>V3.a</name>
<description>Min. and max. Via3 width = 0.19</description>
<categories>
</categories>
</category>
<category>
<name>V3.b</name>
<description>Min. Via3 space = 0.22</description>
<categories>
</categories>
</category>
<category>
<name>V4.a</name>
<description>Min. and max. Via4 width = 0.19</description>
<categories>
</categories>
</category>
<category>
<name>V4.b</name>
<description>Min. Via4 space = 0.22</description>
<categories>
</categories>
</category>
<category>
<name>TV1.a</name>
<description>Min. and max. TopVia1 width = 0.42</description>
<categories>
</categories>
</category>
<category>
<name>TV1.b</name>
<description>Min. TopVia1 space = 0.42</description>
<categories>
</categories>
</category>
<category>
<name>TM1.a</name>
<description>Min. TopMetal1 width = 1.64</description>
<categories>
</categories>
</category>
<category>
<name>TM1.b</name>
<description>Min. TopMetal1 space or notch = 1.64</description>
<categories>
</categories>
</category>
<category>
<name>TM1.c/d</name>
<description>Global TopMetal1 density [%] = 25.00 .. 70.00</description>
<categories>
</categories>
</category>
<category>
<name>TV2.a</name>
<description>Min. and max. TopVia2 width = 0.90</description>
<categories>
</categories>
</category>
<category>
<name>TV2.b</name>
<description>Min. TopVia2 space = 1.06</description>
<categories>
</categories>
</category>
<category>
<name>TM2.a</name>
<description>Min. TopMetal2 width = 2.00</description>
<categories>
</categories>
</category>
<category>
<name>TM2.b</name>
<description>Min. TopMetal2 space or notch = 2.00</description>
<categories>
</categories>
</category>
<category>
<name>TM2.c/d</name>
<description>Global TopMetal2 density [%] = 25.00 .. 70.00</description>
<categories>
</categories>
</category>
<category>
<name>Pas.a</name>
<description>Min. Passiv width = 2.10</description>
<categories>
</categories>
</category>
<category>
<name>Pas.b</name>
<description>Min. Passiv space or notch = 3.50</description>
<categories>
</categories>
</category>
<category>
<name>Pin.a</name>
<description>Min. Activ enclosure of Activ:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.b</name>
<description>Min. GatPoly enclosure of GatPoly:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.e</name>
<description>Min. Metal1 enclosure of Metal1:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.f.M2</name>
<description>Min. Metal2 enclosure of Metal2:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.f.M3</name>
<description>Min. Metal3 enclosure of Metal3:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.f.M4</name>
<description>Min. Metal4 enclosure of Metal4:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.f.M5</name>
<description>Min. Metal5 enclosure of Metal5:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.g</name>
<description>Min. TopMetal1 enclosure of TopMetal1:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.h</name>
<description>Min. TopMetal2 enclosure of TopMetal2:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.a</name>
<description>Min. LBE width = 100.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.b</name>
<description>Max. LBE width = 1500.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.b1</name>
<description>Max. LBE area (µm²) = 250000.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.c</name>
<description>Min. LBE space or notch = 100.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.d</name>
<description>Min. LBE space to inner edge of EdgeSeal = 150.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.h</name>
<description>No LBE ring allowed</description>
<categories>
</categories>
</category>
<category>
<name>LBE.i</name>
<description>Max. global LBE density [%] = 20.00</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.BiWind</name>
<description>Forbidden drawn layer BiWind on GDS layer 3/0 = 3/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.PEmWind</name>
<description>Forbidden drawn layer PEmWind on GDS layer 11/0 = 11/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.BasPoly</name>
<description>Forbidden drawn layer BasPoly on GDS layer 13/0 = 13/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.DeepCo</name>
<description>Forbidden drawn layer DeepCo on GDS layer 35/0 = 35/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.PEmPoly</name>
<description>Forbidden drawn layer PEmPoly on GDS layer 53/0 = 53/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.EmPoly</name>
<description>Forbidden gen./drawn layer EmPoly on GDS layer 53/0 = 53/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.LDMOS</name>
<description>Forbidden drawn layer LDMOS on GDS layer 57/0 = 57/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.PBiWind</name>
<description>Forbidden drawn layer PBiWind on GDS layer 58/0 = 58/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.Flash</name>
<description>Forbidden drawn layer Flash on GDS layer 71/0 = 71/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.ColWind</name>
<description>Forbidden drawn layer ColWind on GDS layer 139/0 = 139/0</description>
<categories>
</categories>
</category>
</categories>
<cells>
<cell>
<name>full_bandgap</name>
<variant/>
<layout-name/>
<references>
</references>
</cell>
</cells>
<items>
</items>
</report-database>

15532
modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/sg13g2_maximal.lyrdb Normal file
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688
modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/sg13g2_minimal.lyrdb Normal file
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@ -0,0 +1,688 @@
<?xml version="1.0" encoding="utf-8"?>
<report-database>
<description>design rules: sg13g2_minimal | layout cell: two_stage_OTA_layout</description>
<original-file>two_stage_OTA_layout.gds</original-file>
<generator>drc: script='/home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_minimal.lydrc'</generator>
<top-cell>two_stage_OTA_layout</top-cell>
<tags>
</tags>
<categories>
<category>
<name>Act.a</name>
<description>Min. Activ width = 0.15</description>
<categories>
</categories>
</category>
<category>
<name>Act.b</name>
<description>Min. Activ space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>AFil.g/g1</name>
<description>Global Activ density [%] = 35.00 .. 55.00</description>
<categories>
</categories>
</category>
<category>
<name>AFil.g2/g3</name>
<description>Activ coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 65.00</description>
<categories>
</categories>
</category>
<category>
<name>TGO.f</name>
<description>Min. ThickGateOx width = 0.86</description>
<categories>
</categories>
</category>
<category>
<name>Gat.a</name>
<description>Min. GatPoly width = 0.13</description>
<categories>
</categories>
</category>
<category>
<name>Gat.b</name>
<description>Min. GatPoly space or notch = 0.18</description>
<categories>
</categories>
</category>
<category>
<name>Gat.d</name>
<description>Min. GatPoly space to Activ = 0.07</description>
<categories>
</categories>
</category>
<category>
<name>GFil.g</name>
<description>Min. global GatPoly density [%] = 15.00</description>
<categories>
</categories>
</category>
<category>
<name>Cnt.a</name>
<description>Min. and max. Cont width = 0.16</description>
<categories>
</categories>
</category>
<category>
<name>Cnt.b</name>
<description>Min. Cont space = 0.18</description>
<categories>
</categories>
</category>
<category>
<name>M1.a</name>
<description>Min. Metal1 width = 0.16</description>
<categories>
</categories>
</category>
<category>
<name>M1.b</name>
<description>Min. Metal1 space or notch = 0.18</description>
<categories>
</categories>
</category>
<category>
<name>M1.j/k</name>
<description>Global Metal1 density [%] = 35.0 .. 60.0</description>
<categories>
</categories>
</category>
<category>
<name>M2.a</name>
<description>Min. Metal2 width = 0.20</description>
<categories>
</categories>
</category>
<category>
<name>M2.b</name>
<description>Min. Metal2 space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>M2.j/k</name>
<description>Global Metal2 density [%] = 35.00 .. 60.00</description>
<categories>
</categories>
</category>
<category>
<name>M3.a</name>
<description>Min. Metal3 width = 0.20</description>
<categories>
</categories>
</category>
<category>
<name>M3.b</name>
<description>Min. Metal3 space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>M3.j/k</name>
<description>Global Metal3 density [%] = 35.00 .. 60.00</description>
<categories>
</categories>
</category>
<category>
<name>M4.a</name>
<description>Min. Metal4 width = 0.20</description>
<categories>
</categories>
</category>
<category>
<name>M4.b</name>
<description>Min. Metal4 space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>M4.j/k</name>
<description>Global Metal4 density [%] = 35.00 .. 60.00</description>
<categories>
</categories>
</category>
<category>
<name>M5.a</name>
<description>Min. Metal5 width = 0.20</description>
<categories>
</categories>
</category>
<category>
<name>M5.b</name>
<description>Min. Metal5 space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>M5.j/k</name>
<description>Global Metal5 density [%] = 35.00 .. 60.00</description>
<categories>
</categories>
</category>
<category>
<name>M1Fil.h/k</name>
<description>Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>M2Fil.h/k</name>
<description>Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>M3Fil.h/k</name>
<description>Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>M4Fil.h/k</name>
<description>Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>M5Fil.h/k</name>
<description>Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>V1.a</name>
<description>Min. and max. Via1 width = 0.19</description>
<categories>
</categories>
</category>
<category>
<name>V1.b</name>
<description>Min. Via1 space = 0.22</description>
<categories>
</categories>
</category>
<category>
<name>V2.a</name>
<description>Min. and max. Via2 width = 0.19</description>
<categories>
</categories>
</category>
<category>
<name>V2.b</name>
<description>Min. Via2 space = 0.22</description>
<categories>
</categories>
</category>
<category>
<name>V3.a</name>
<description>Min. and max. Via3 width = 0.19</description>
<categories>
</categories>
</category>
<category>
<name>V3.b</name>
<description>Min. Via3 space = 0.22</description>
<categories>
</categories>
</category>
<category>
<name>V4.a</name>
<description>Min. and max. Via4 width = 0.19</description>
<categories>
</categories>
</category>
<category>
<name>V4.b</name>
<description>Min. Via4 space = 0.22</description>
<categories>
</categories>
</category>
<category>
<name>TV1.a</name>
<description>Min. and max. TopVia1 width = 0.42</description>
<categories>
</categories>
</category>
<category>
<name>TV1.b</name>
<description>Min. TopVia1 space = 0.42</description>
<categories>
</categories>
</category>
<category>
<name>TM1.a</name>
<description>Min. TopMetal1 width = 1.64</description>
<categories>
</categories>
</category>
<category>
<name>TM1.b</name>
<description>Min. TopMetal1 space or notch = 1.64</description>
<categories>
</categories>
</category>
<category>
<name>TM1.c/d</name>
<description>Global TopMetal1 density [%] = 25.00 .. 70.00</description>
<categories>
</categories>
</category>
<category>
<name>TV2.a</name>
<description>Min. and max. TopVia2 width = 0.90</description>
<categories>
</categories>
</category>
<category>
<name>TV2.b</name>
<description>Min. TopVia2 space = 1.06</description>
<categories>
</categories>
</category>
<category>
<name>TM2.a</name>
<description>Min. TopMetal2 width = 2.00</description>
<categories>
</categories>
</category>
<category>
<name>TM2.b</name>
<description>Min. TopMetal2 space or notch = 2.00</description>
<categories>
</categories>
</category>
<category>
<name>TM2.c/d</name>
<description>Global TopMetal2 density [%] = 25.00 .. 70.00</description>
<categories>
</categories>
</category>
<category>
<name>Pas.a</name>
<description>Min. Passiv width = 2.10</description>
<categories>
</categories>
</category>
<category>
<name>Pas.b</name>
<description>Min. Passiv space or notch = 3.50</description>
<categories>
</categories>
</category>
<category>
<name>Pin.a</name>
<description>Min. Activ enclosure of Activ:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.b</name>
<description>Min. GatPoly enclosure of GatPoly:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.e</name>
<description>Min. Metal1 enclosure of Metal1:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.f.M2</name>
<description>Min. Metal2 enclosure of Metal2:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.f.M3</name>
<description>Min. Metal3 enclosure of Metal3:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.f.M4</name>
<description>Min. Metal4 enclosure of Metal4:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.f.M5</name>
<description>Min. Metal5 enclosure of Metal5:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.g</name>
<description>Min. TopMetal1 enclosure of TopMetal1:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.h</name>
<description>Min. TopMetal2 enclosure of TopMetal2:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.a</name>
<description>Min. LBE width = 100.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.b</name>
<description>Max. LBE width = 1500.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.b1</name>
<description>Max. LBE area (µm²) = 250000.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.c</name>
<description>Min. LBE space or notch = 100.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.d</name>
<description>Min. LBE space to inner edge of EdgeSeal = 150.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.h</name>
<description>No LBE ring allowed</description>
<categories>
</categories>
</category>
<category>
<name>LBE.i</name>
<description>Max. global LBE density [%] = 20.00</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.BiWind</name>
<description>Forbidden drawn layer BiWind on GDS layer 3/0 = 3/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.PEmWind</name>
<description>Forbidden drawn layer PEmWind on GDS layer 11/0 = 11/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.BasPoly</name>
<description>Forbidden drawn layer BasPoly on GDS layer 13/0 = 13/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.DeepCo</name>
<description>Forbidden drawn layer DeepCo on GDS layer 35/0 = 35/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.PEmPoly</name>
<description>Forbidden drawn layer PEmPoly on GDS layer 53/0 = 53/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.EmPoly</name>
<description>Forbidden gen./drawn layer EmPoly on GDS layer 53/0 = 53/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.LDMOS</name>
<description>Forbidden drawn layer LDMOS on GDS layer 57/0 = 57/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.PBiWind</name>
<description>Forbidden drawn layer PBiWind on GDS layer 58/0 = 58/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.Flash</name>
<description>Forbidden drawn layer Flash on GDS layer 71/0 = 71/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.ColWind</name>
<description>Forbidden drawn layer ColWind on GDS layer 139/0 = 139/0</description>
<categories>
</categories>
</category>
</categories>
<cells>
<cell>
<name>two_stage_OTA_layout</name>
<variant/>
<layout-name/>
<references>
</references>
</cell>
</cells>
<items>
<item>
<tags/>
<category>'M1.b'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>edge-pair: (59.965,6.005;69.375,6.005)|(69.375,6.13;59.965,6.13)</value>
</values>
</item>
<item>
<tags/>
<category>'M1.b'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>edge-pair: (59.835,6.005;69.505,6.005)|(69.375,6.13;59.965,6.13)</value>
</values>
</item>
<item>
<tags/>
<category>'M1.j/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'M2.b'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>edge-pair: (59.965,6.005;69.375,6.005)|(69.375,6.13;59.965,6.13)</value>
</values>
</item>
<item>
<tags/>
<category>'M2.b'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>edge-pair: (59.796,6.005;69.375,6.005)|(69.375,6.13;59.965,6.13)</value>
</values>
</item>
<item>
<tags/>
<category>'M2.j/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'M3.j/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'M4.j/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'M5.j/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'M1Fil.h/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'M2Fil.h/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'M3Fil.h/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'M4Fil.h/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'M5Fil.h/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'TM1.c/d'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'TM2.c/d'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'Pin.f.M2'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (27.925,3.955;27.925,4.285;27.985,4.285;27.985,3.955)</value>
</values>
</item>
</items>
</report-database>

2
modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/two_stage_OTA_layout_extracted.cir
View File

@ -1,4 +1,4 @@
* Extracted by KLayout with SG13G2 LVS runset on : 28/03/2025 08:06
* Extracted by KLayout with SG13G2 LVS runset on : 17/07/2025 11:31
.SUBCKT two_stage_OTA_layout vss vdd dn3 iout vout dn2 v+ v\x2d vss$1 dn4
M$1 vss dn3 dn3 vss sg13_lv_nmos L=9.75u W=0.72u AS=0.2448p AD=0.2448p PS=2.12u

100
modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/comparator_tb.sch
View File

@ -12,7 +12,7 @@ ypos2=2
divy=5
subdivy=1
unity=1
x1=-1e-07
x1=0
divx=5
subdivx=4
@ -24,10 +24,10 @@ dataset=-1
unitx=1
logx=0
logy=0
x2=9e-07
x2=1e-06
color=4
node=clk}
B 2 20 -885 820 -485 {flags=graph
B 2 20 -855 820 -455 {flags=graph
y1=0.59
y2=0.61
ypos1=0
@ -35,7 +35,7 @@ ypos2=2
divy=5
subdivy=1
unity=1
x1=-1e-07
x1=0
divx=5
subdivx=4
@ -47,7 +47,7 @@ dataset=-1
unitx=1
logx=0
logy=0
x2=9e-07
x2=1e-06
color=4
@ -60,7 +60,7 @@ ypos2=2
divy=5
subdivy=1
unity=1
x1=-1e-07
x1=0
divx=5
subdivx=4
@ -72,20 +72,20 @@ dataset=-1
unitx=1
logx=0
logy=0
x2=9e-07
x2=1e-06
color=4
node=vout}
B 2 850 -805 1650 -405 {flags=graph
y1=-0.7005027
y2=1.1959773
y1=1.1
y2=1.2
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=-1e-07
x1=0
divx=5
subdivx=4
@ -97,7 +97,7 @@ dataset=-1
unitx=1
logx=0
logy=0
x2=9e-07
x2=1e-06
color=4
node=outp}
@ -109,7 +109,7 @@ ypos2=2
divy=5
subdivy=1
unity=1
x1=-1e-07
x1=0
divx=5
subdivx=4
@ -121,7 +121,7 @@ dataset=-1
unitx=1
logx=0
logy=0
x2=9e-07
x2=1e-06
color=4
@ -166,8 +166,6 @@ N -610 -80 -570 -80 {
lab=GND}
N -540 -100 -540 -80 {
lab=GND}
N 80 -300 80 -280 {
lab=vinp}
N 60 -280 80 -280 {
lab=vinp}
N 80 -160 80 -140 {
@ -176,37 +174,44 @@ N 60 -160 80 -160 {
lab=vbias}
N 80 -80 80 -60 {
lab=GND}
N 80 -380 80 -360 {
lab=GND}
N 460 -150 460 -140 {
lab=GND}
N 460 -300 460 -290 {
lab=GND}
C {devices/code_shown.sym} -675 -490 0 0 {name=MODEL only_toplevel=false
N 80 -300 80 -280 {
lab=vinp}
N 80 -380 80 -360 {
lab=GND}
C {devices/code_shown.sym} -775 -550 0 0 {name=MODEL only_toplevel=false
format="tcleval( @value )"
value="
.lib cornerMOSlv.lib mos_tt
"}
C {devices/code_shown.sym} -685 -780 0 0 {name=NGSPICE only_toplevel=false
C {devices/code_shown.sym} -865 -1040 0 0 {name=NGSPICE only_toplevel=false
value="
.include comparator_tb.save
.param temp=27
.param clock = 100e6 ; 100 MHz clock
.param period = \{1/clock\}
.param num_cycles = 100
.param tr = \{num_cycles * period\}
.control
save all
* Operating point simulation
op
.param clock = 100e6 ; 100 MHz clock
.param period = 1 / clock
.param num_cycles = 100 ; number of evaluation cycles
.param tr = num_cycles * period
write comparator_tb.raw
set appendwrite
* Transient analysis
tran 500p 1u
.save all
let vindiff = (v(vinp))-(v(vbias))
let vindiff = v(vinp) - v(vbias)
let clk = v(clk)
let vout = (v(outp))-(v(outm))
write output_file.raw
let vout = v(outp) - v(outm)
write comparator_tb.raw
.endc
"}
C {launcher.sym} -160 -855 0 0 {name=h5
descr="load waves"
tclcommand="xschem raw_read $netlist_dir/output_file.raw tran"
}
C {vsource.sym} -610 -130 0 0 {name=V3 value="DC 1.2"}
C {vsource.sym} -540 -130 0 0 {name=V4 value="DC 0.6"}
C {gnd.sym} -310 -70 0 0 {name=l1 lab=GND}
@ -250,3 +255,36 @@ device="ceramic capacitor"}
C {gnd.sym} 460 -140 0 0 {name=l6 lab=GND}
C {gnd.sym} 460 -300 2 0 {name=l7 lab=GND}
C {dynamic_comparator.sym} 270 -220 0 0 {name=x1}
C {sg13g2_pr/annotate_fet_params.sym} -240 -1070 0 0 {name=annot1 ref=M3}
C {devices/launcher.sym} -210 -810 0 0 {name=h1
descr="OP annotate"
tclcommand="xschem annotate_op"
}
C {launcher.sym} -210 -850 0 0 {name=h5
descr="load waves"
tclcommand="xschem raw_read $netlist_dir/comparator_tb.raw tran"
}
C {launcher.sym} -210 -765 0 0 {name=h2
descr=SimulateNGSPICE
tclcommand="
# Setup the default simulation commands if not already set up
# for example by already launched simulations.
set_sim_defaults
puts $sim(spice,1,cmd)
# Change the Xyce command. In the spice category there are currently
# 5 commands (0, 1, 2, 3, 4). Command 3 is the Xyce batch
# you can get the number by querying $sim(spice,n)
set sim(spice,1,cmd) \{ngspice \\"$N\\" -a\}
# change the simulator to be used (Xyce)
set sim(spice,default) 0
# Create FET and BIP .save file
mkdir -p $netlist_dir
write_data [save_params] $netlist_dir/[file rootname [file tail [xschem get current_name]]].save
# run netlist and simulation
xschem netlist
simulate
"}

122
modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/simulations/.save Normal file
View File

@ -0,0 +1,122 @@
* Place this .save file with a .include line in your testbench
.save @n.x1.xm13.nsg13_lv_pmos[ids]
.save @n.x1.xm13.nsg13_lv_pmos[gm]
.save @n.x1.xm13.nsg13_lv_pmos[gds]
.save @n.x1.xm13.nsg13_lv_pmos[vth]
.save @n.x1.xm13.nsg13_lv_pmos[vgs]
.save @n.x1.xm13.nsg13_lv_pmos[vdss]
.save @n.x1.xm13.nsg13_lv_pmos[vds]
.save @n.x1.xm13.nsg13_lv_pmos[cgg]
.save @n.x1.xm13.nsg13_lv_pmos[cgsol]
.save @n.x1.xm13.nsg13_lv_pmos[cgdol]
.save @n.x1.xm3.nsg13_lv_pmos[ids]
.save @n.x1.xm3.nsg13_lv_pmos[gm]
.save @n.x1.xm3.nsg13_lv_pmos[gds]
.save @n.x1.xm3.nsg13_lv_pmos[vth]
.save @n.x1.xm3.nsg13_lv_pmos[vgs]
.save @n.x1.xm3.nsg13_lv_pmos[vdss]
.save @n.x1.xm3.nsg13_lv_pmos[vds]
.save @n.x1.xm3.nsg13_lv_pmos[cgg]
.save @n.x1.xm3.nsg13_lv_pmos[cgsol]
.save @n.x1.xm3.nsg13_lv_pmos[cgdol]
.save @n.x1.xm2.nsg13_lv_pmos[ids]
.save @n.x1.xm2.nsg13_lv_pmos[gm]
.save @n.x1.xm2.nsg13_lv_pmos[gds]
.save @n.x1.xm2.nsg13_lv_pmos[vth]
.save @n.x1.xm2.nsg13_lv_pmos[vgs]
.save @n.x1.xm2.nsg13_lv_pmos[vdss]
.save @n.x1.xm2.nsg13_lv_pmos[vds]
.save @n.x1.xm2.nsg13_lv_pmos[cgg]
.save @n.x1.xm2.nsg13_lv_pmos[cgsol]
.save @n.x1.xm2.nsg13_lv_pmos[cgdol]
.save @n.x1.xm1.nsg13_lv_pmos[ids]
.save @n.x1.xm1.nsg13_lv_pmos[gm]
.save @n.x1.xm1.nsg13_lv_pmos[gds]
.save @n.x1.xm1.nsg13_lv_pmos[vth]
.save @n.x1.xm1.nsg13_lv_pmos[vgs]
.save @n.x1.xm1.nsg13_lv_pmos[vdss]
.save @n.x1.xm1.nsg13_lv_pmos[vds]
.save @n.x1.xm1.nsg13_lv_pmos[cgg]
.save @n.x1.xm1.nsg13_lv_pmos[cgsol]
.save @n.x1.xm1.nsg13_lv_pmos[cgdol]
.save @n.x1.xm4.nsg13_lv_pmos[ids]
.save @n.x1.xm4.nsg13_lv_pmos[gm]
.save @n.x1.xm4.nsg13_lv_pmos[gds]
.save @n.x1.xm4.nsg13_lv_pmos[vth]
.save @n.x1.xm4.nsg13_lv_pmos[vgs]
.save @n.x1.xm4.nsg13_lv_pmos[vdss]
.save @n.x1.xm4.nsg13_lv_pmos[vds]
.save @n.x1.xm4.nsg13_lv_pmos[cgg]
.save @n.x1.xm4.nsg13_lv_pmos[cgsol]
.save @n.x1.xm4.nsg13_lv_pmos[cgdol]
.save @n.x1.xm5.nsg13_lv_pmos[ids]
.save @n.x1.xm5.nsg13_lv_pmos[gm]
.save @n.x1.xm5.nsg13_lv_pmos[gds]
.save @n.x1.xm5.nsg13_lv_pmos[vth]
.save @n.x1.xm5.nsg13_lv_pmos[vgs]
.save @n.x1.xm5.nsg13_lv_pmos[vdss]
.save @n.x1.xm5.nsg13_lv_pmos[vds]
.save @n.x1.xm5.nsg13_lv_pmos[cgg]
.save @n.x1.xm5.nsg13_lv_pmos[cgsol]
.save @n.x1.xm5.nsg13_lv_pmos[cgdol]
.save @n.x1.xm11.nsg13_lv_nmos[ids]
.save @n.x1.xm11.nsg13_lv_nmos[gm]
.save @n.x1.xm11.nsg13_lv_nmos[gds]
.save @n.x1.xm11.nsg13_lv_nmos[vth]
.save @n.x1.xm11.nsg13_lv_nmos[vgs]
.save @n.x1.xm11.nsg13_lv_nmos[vdss]
.save @n.x1.xm11.nsg13_lv_nmos[vds]
.save @n.x1.xm11.nsg13_lv_nmos[cgg]
.save @n.x1.xm11.nsg13_lv_nmos[cgsol]
.save @n.x1.xm11.nsg13_lv_nmos[cgdol]
.save @n.x1.xm12.nsg13_lv_nmos[ids]
.save @n.x1.xm12.nsg13_lv_nmos[gm]
.save @n.x1.xm12.nsg13_lv_nmos[gds]
.save @n.x1.xm12.nsg13_lv_nmos[vth]
.save @n.x1.xm12.nsg13_lv_nmos[vgs]
.save @n.x1.xm12.nsg13_lv_nmos[vdss]
.save @n.x1.xm12.nsg13_lv_nmos[vds]
.save @n.x1.xm12.nsg13_lv_nmos[cgg]
.save @n.x1.xm12.nsg13_lv_nmos[cgsol]
.save @n.x1.xm12.nsg13_lv_nmos[cgdol]
.save @n.x1.xm6.nsg13_lv_nmos[ids]
.save @n.x1.xm6.nsg13_lv_nmos[gm]
.save @n.x1.xm6.nsg13_lv_nmos[gds]
.save @n.x1.xm6.nsg13_lv_nmos[vth]
.save @n.x1.xm6.nsg13_lv_nmos[vgs]
.save @n.x1.xm6.nsg13_lv_nmos[vdss]
.save @n.x1.xm6.nsg13_lv_nmos[vds]
.save @n.x1.xm6.nsg13_lv_nmos[cgg]
.save @n.x1.xm6.nsg13_lv_nmos[cgsol]
.save @n.x1.xm6.nsg13_lv_nmos[cgdol]
.save @n.x1.xm10.nsg13_lv_nmos[ids]
.save @n.x1.xm10.nsg13_lv_nmos[gm]
.save @n.x1.xm10.nsg13_lv_nmos[gds]
.save @n.x1.xm10.nsg13_lv_nmos[vth]
.save @n.x1.xm10.nsg13_lv_nmos[vgs]
.save @n.x1.xm10.nsg13_lv_nmos[vdss]
.save @n.x1.xm10.nsg13_lv_nmos[vds]
.save @n.x1.xm10.nsg13_lv_nmos[cgg]
.save @n.x1.xm10.nsg13_lv_nmos[cgsol]
.save @n.x1.xm10.nsg13_lv_nmos[cgdol]
.save @n.x1.xm7.nsg13_lv_nmos[ids]
.save @n.x1.xm7.nsg13_lv_nmos[gm]
.save @n.x1.xm7.nsg13_lv_nmos[gds]
.save @n.x1.xm7.nsg13_lv_nmos[vth]
.save @n.x1.xm7.nsg13_lv_nmos[vgs]
.save @n.x1.xm7.nsg13_lv_nmos[vdss]
.save @n.x1.xm7.nsg13_lv_nmos[vds]
.save @n.x1.xm7.nsg13_lv_nmos[cgg]
.save @n.x1.xm7.nsg13_lv_nmos[cgsol]
.save @n.x1.xm7.nsg13_lv_nmos[cgdol]
.save @n.x1.xm8.nsg13_lv_nmos[ids]
.save @n.x1.xm8.nsg13_lv_nmos[gm]
.save @n.x1.xm8.nsg13_lv_nmos[gds]
.save @n.x1.xm8.nsg13_lv_nmos[vth]
.save @n.x1.xm8.nsg13_lv_nmos[vgs]
.save @n.x1.xm8.nsg13_lv_nmos[vdss]
.save @n.x1.xm8.nsg13_lv_nmos[vds]
.save @n.x1.xm8.nsg13_lv_nmos[cgg]
.save @n.x1.xm8.nsg13_lv_nmos[cgsol]
.save @n.x1.xm8.nsg13_lv_nmos[cgdol]

122
modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/simulations/comparator_tb.save Normal file
View File

@ -0,0 +1,122 @@
* Place this .save file with a .include line in your testbench
.save @n.x1.xm13.nsg13_lv_pmos[ids]
.save @n.x1.xm13.nsg13_lv_pmos[gm]
.save @n.x1.xm13.nsg13_lv_pmos[gds]
.save @n.x1.xm13.nsg13_lv_pmos[vth]
.save @n.x1.xm13.nsg13_lv_pmos[vgs]
.save @n.x1.xm13.nsg13_lv_pmos[vdss]
.save @n.x1.xm13.nsg13_lv_pmos[vds]
.save @n.x1.xm13.nsg13_lv_pmos[cgg]
.save @n.x1.xm13.nsg13_lv_pmos[cgsol]
.save @n.x1.xm13.nsg13_lv_pmos[cgdol]
.save @n.x1.xm3.nsg13_lv_pmos[ids]
.save @n.x1.xm3.nsg13_lv_pmos[gm]
.save @n.x1.xm3.nsg13_lv_pmos[gds]
.save @n.x1.xm3.nsg13_lv_pmos[vth]
.save @n.x1.xm3.nsg13_lv_pmos[vgs]
.save @n.x1.xm3.nsg13_lv_pmos[vdss]
.save @n.x1.xm3.nsg13_lv_pmos[vds]
.save @n.x1.xm3.nsg13_lv_pmos[cgg]
.save @n.x1.xm3.nsg13_lv_pmos[cgsol]
.save @n.x1.xm3.nsg13_lv_pmos[cgdol]
.save @n.x1.xm2.nsg13_lv_pmos[ids]
.save @n.x1.xm2.nsg13_lv_pmos[gm]
.save @n.x1.xm2.nsg13_lv_pmos[gds]
.save @n.x1.xm2.nsg13_lv_pmos[vth]
.save @n.x1.xm2.nsg13_lv_pmos[vgs]
.save @n.x1.xm2.nsg13_lv_pmos[vdss]
.save @n.x1.xm2.nsg13_lv_pmos[vds]
.save @n.x1.xm2.nsg13_lv_pmos[cgg]
.save @n.x1.xm2.nsg13_lv_pmos[cgsol]
.save @n.x1.xm2.nsg13_lv_pmos[cgdol]
.save @n.x1.xm1.nsg13_lv_pmos[ids]
.save @n.x1.xm1.nsg13_lv_pmos[gm]
.save @n.x1.xm1.nsg13_lv_pmos[gds]
.save @n.x1.xm1.nsg13_lv_pmos[vth]
.save @n.x1.xm1.nsg13_lv_pmos[vgs]
.save @n.x1.xm1.nsg13_lv_pmos[vdss]
.save @n.x1.xm1.nsg13_lv_pmos[vds]
.save @n.x1.xm1.nsg13_lv_pmos[cgg]
.save @n.x1.xm1.nsg13_lv_pmos[cgsol]
.save @n.x1.xm1.nsg13_lv_pmos[cgdol]
.save @n.x1.xm4.nsg13_lv_pmos[ids]
.save @n.x1.xm4.nsg13_lv_pmos[gm]
.save @n.x1.xm4.nsg13_lv_pmos[gds]
.save @n.x1.xm4.nsg13_lv_pmos[vth]
.save @n.x1.xm4.nsg13_lv_pmos[vgs]
.save @n.x1.xm4.nsg13_lv_pmos[vdss]
.save @n.x1.xm4.nsg13_lv_pmos[vds]
.save @n.x1.xm4.nsg13_lv_pmos[cgg]
.save @n.x1.xm4.nsg13_lv_pmos[cgsol]
.save @n.x1.xm4.nsg13_lv_pmos[cgdol]
.save @n.x1.xm5.nsg13_lv_pmos[ids]
.save @n.x1.xm5.nsg13_lv_pmos[gm]
.save @n.x1.xm5.nsg13_lv_pmos[gds]
.save @n.x1.xm5.nsg13_lv_pmos[vth]
.save @n.x1.xm5.nsg13_lv_pmos[vgs]
.save @n.x1.xm5.nsg13_lv_pmos[vdss]
.save @n.x1.xm5.nsg13_lv_pmos[vds]
.save @n.x1.xm5.nsg13_lv_pmos[cgg]
.save @n.x1.xm5.nsg13_lv_pmos[cgsol]
.save @n.x1.xm5.nsg13_lv_pmos[cgdol]
.save @n.x1.xm11.nsg13_lv_nmos[ids]
.save @n.x1.xm11.nsg13_lv_nmos[gm]
.save @n.x1.xm11.nsg13_lv_nmos[gds]
.save @n.x1.xm11.nsg13_lv_nmos[vth]
.save @n.x1.xm11.nsg13_lv_nmos[vgs]
.save @n.x1.xm11.nsg13_lv_nmos[vdss]
.save @n.x1.xm11.nsg13_lv_nmos[vds]
.save @n.x1.xm11.nsg13_lv_nmos[cgg]
.save @n.x1.xm11.nsg13_lv_nmos[cgsol]
.save @n.x1.xm11.nsg13_lv_nmos[cgdol]
.save @n.x1.xm12.nsg13_lv_nmos[ids]
.save @n.x1.xm12.nsg13_lv_nmos[gm]
.save @n.x1.xm12.nsg13_lv_nmos[gds]
.save @n.x1.xm12.nsg13_lv_nmos[vth]
.save @n.x1.xm12.nsg13_lv_nmos[vgs]
.save @n.x1.xm12.nsg13_lv_nmos[vdss]
.save @n.x1.xm12.nsg13_lv_nmos[vds]
.save @n.x1.xm12.nsg13_lv_nmos[cgg]
.save @n.x1.xm12.nsg13_lv_nmos[cgsol]
.save @n.x1.xm12.nsg13_lv_nmos[cgdol]
.save @n.x1.xm6.nsg13_lv_nmos[ids]
.save @n.x1.xm6.nsg13_lv_nmos[gm]
.save @n.x1.xm6.nsg13_lv_nmos[gds]
.save @n.x1.xm6.nsg13_lv_nmos[vth]
.save @n.x1.xm6.nsg13_lv_nmos[vgs]
.save @n.x1.xm6.nsg13_lv_nmos[vdss]
.save @n.x1.xm6.nsg13_lv_nmos[vds]
.save @n.x1.xm6.nsg13_lv_nmos[cgg]
.save @n.x1.xm6.nsg13_lv_nmos[cgsol]
.save @n.x1.xm6.nsg13_lv_nmos[cgdol]
.save @n.x1.xm10.nsg13_lv_nmos[ids]
.save @n.x1.xm10.nsg13_lv_nmos[gm]
.save @n.x1.xm10.nsg13_lv_nmos[gds]
.save @n.x1.xm10.nsg13_lv_nmos[vth]
.save @n.x1.xm10.nsg13_lv_nmos[vgs]
.save @n.x1.xm10.nsg13_lv_nmos[vdss]
.save @n.x1.xm10.nsg13_lv_nmos[vds]
.save @n.x1.xm10.nsg13_lv_nmos[cgg]
.save @n.x1.xm10.nsg13_lv_nmos[cgsol]
.save @n.x1.xm10.nsg13_lv_nmos[cgdol]
.save @n.x1.xm7.nsg13_lv_nmos[ids]
.save @n.x1.xm7.nsg13_lv_nmos[gm]
.save @n.x1.xm7.nsg13_lv_nmos[gds]
.save @n.x1.xm7.nsg13_lv_nmos[vth]
.save @n.x1.xm7.nsg13_lv_nmos[vgs]
.save @n.x1.xm7.nsg13_lv_nmos[vdss]
.save @n.x1.xm7.nsg13_lv_nmos[vds]
.save @n.x1.xm7.nsg13_lv_nmos[cgg]
.save @n.x1.xm7.nsg13_lv_nmos[cgsol]
.save @n.x1.xm7.nsg13_lv_nmos[cgdol]
.save @n.x1.xm8.nsg13_lv_nmos[ids]
.save @n.x1.xm8.nsg13_lv_nmos[gm]
.save @n.x1.xm8.nsg13_lv_nmos[gds]
.save @n.x1.xm8.nsg13_lv_nmos[vth]
.save @n.x1.xm8.nsg13_lv_nmos[vgs]
.save @n.x1.xm8.nsg13_lv_nmos[vdss]
.save @n.x1.xm8.nsg13_lv_nmos[vds]
.save @n.x1.xm8.nsg13_lv_nmos[cgg]
.save @n.x1.xm8.nsg13_lv_nmos[cgsol]
.save @n.x1.xm8.nsg13_lv_nmos[cgdol]

12
modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/simulations/dc_lv_nmos.save Normal file
View File

@ -0,0 +1,12 @@
* Place this .save file with a .include line in your testbench
.save @n.xm1.nsg13_lv_nmos[ids]
.save @n.xm1.nsg13_lv_nmos[gm]
.save @n.xm1.nsg13_lv_nmos[gds]
.save @n.xm1.nsg13_lv_nmos[vth]
.save @n.xm1.nsg13_lv_nmos[vgs]
.save @n.xm1.nsg13_lv_nmos[vdss]
.save @n.xm1.nsg13_lv_nmos[vds]
.save @n.xm1.nsg13_lv_nmos[cgg]
.save @n.xm1.nsg13_lv_nmos[cgsol]
.save @n.xm1.nsg13_lv_nmos[cgdol]

32
modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/simulations/inv_mc_tb.save Normal file
View File

@ -0,0 +1,32 @@
* Place this .save file with a .include line in your testbench
.save @n.xm1.nsg13_lv_nmos[ids]
.save @n.xm1.nsg13_lv_nmos[gm]
.save @n.xm1.nsg13_lv_nmos[gds]
.save @n.xm1.nsg13_lv_nmos[vth]
.save @n.xm1.nsg13_lv_nmos[vgs]
.save @n.xm1.nsg13_lv_nmos[vdss]
.save @n.xm1.nsg13_lv_nmos[vds]
.save @n.xm1.nsg13_lv_nmos[cgg]
.save @n.xm1.nsg13_lv_nmos[cgsol]
.save @n.xm1.nsg13_lv_nmos[cgdol]
.save @n.xm2.nsg13_lv_pmos[ids]
.save @n.xm2.nsg13_lv_pmos[gm]
.save @n.xm2.nsg13_lv_pmos[gds]
.save @n.xm2.nsg13_lv_pmos[vth]
.save @n.xm2.nsg13_lv_pmos[vgs]
.save @n.xm2.nsg13_lv_pmos[vdss]
.save @n.xm2.nsg13_lv_pmos[vds]
.save @n.xm2.nsg13_lv_pmos[cgg]
.save @n.xm2.nsg13_lv_pmos[cgsol]
.save @n.xm2.nsg13_lv_pmos[cgdol]
.save @n.xm3.nsg13_lv_nmos[ids]
.save @n.xm3.nsg13_lv_nmos[gm]
.save @n.xm3.nsg13_lv_nmos[gds]
.save @n.xm3.nsg13_lv_nmos[vth]
.save @n.xm3.nsg13_lv_nmos[vgs]
.save @n.xm3.nsg13_lv_nmos[vdss]
.save @n.xm3.nsg13_lv_nmos[vds]
.save @n.xm3.nsg13_lv_nmos[cgg]
.save @n.xm3.nsg13_lv_nmos[cgsol]
.save @n.xm3.nsg13_lv_nmos[cgdol]

BIN
modules/module_3_8_bit_SAR_ADC/part_5_layout/.media/inverter_layout.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 53 KiB

BIN
modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/layout/DIFF_COMPARATOR.gds Normal file
View File

Binary file not shown.

BIN
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/input_pair_cm.gds → modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/layout/misc/input_pair/input_pair_cm.gds
View File

Binary file not shown.

9
modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/layout/misc/input_pair/input_pair_cm_extracted.cir Normal file
View File

@ -0,0 +1,9 @@
* Extracted by KLayout with SG13G2 LVS runset on : 14/07/2025 15:44
.SUBCKT input_pair_cm vdd Drain2 Drain1 top
M$1 top \$9 Drain1 \$2 sg13_lv_pmos L=0.2u W=32u AS=8.48p AD=8.48p PS=52.24u
+ PD=52.24u
M$3 top \$8 Drain2 \$2 sg13_lv_pmos L=0.2u W=32u AS=8.48p AD=8.48p PS=52.24u
+ PD=52.24u
R$17 \$2 vdd ntap1 A=15.376p P=99.2u
.ENDS input_pair_cm

30
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/schematic_mod/input_pair_cm.sch → modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/layout/misc/input_pair/schematic_mod/input_pair_cm.sch
View File

@ -5,44 +5,44 @@ V {}
S {}
E {}
N 490 -650 490 -600 {
lab=#net1}
lab=top}
N 810 -650 810 -600 {
lab=#net1}
lab=top}
N 810 -540 810 -470 {
lab=Drain2}
N 650 -650 810 -650 {
lab=#net1}
lab=top}
N 650 -710 650 -650 {
lab=#net1}
lab=top}
N 490 -650 650 -650 {
lab=#net1}
lab=top}
N 650 -570 810 -570 {
lab=#net2}
lab=#net1}
N 490 -540 490 -470 {
lab=Drain1}
N 440 -570 450 -570 {
lab=v+}
N 850 -570 860 -570 {
lab=v-}
N 650 -570 650 -550 {lab=#net2}
N 650 -570 650 -550 {lab=#net1}
N 490 -570 650 -570 {
lab=#net2}
N 650 -490 650 -470 {lab=#net3}
lab=#net1}
N 650 -490 650 -470 {lab=vdd}
C {ipin.sym} 440 -570 0 0 {name=p3 lab=v+}
C {ipin.sym} 860 -570 0 1 {name=p4 lab=v-}
C {sg13g2_pr/sg13_lv_pmos.sym} 470 -570 0 0 {name=M2
l=200n
w=32u
ng=4
m=1
w=8u
ng=2
m=4
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 830 -570 0 1 {name=M1
l=200n
w=32u
ng=4
m=1
w=8u
ng=2
m=4
model=sg13_lv_pmos
spiceprefix=X
}

BIN
modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/layout/misc/load/load.gds Normal file
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126
modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/layout/misc/load/schematic_mod/load.sch Normal file
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@ -0,0 +1,126 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 720 -270 720 -230 {
lab=Drain2}
N 810 -270 900 -270 {
lab=Drain2}
N 900 -270 900 -230 {
lab=Drain2}
N 810 -470 810 -270 {
lab=Drain2}
N 720 -270 810 -270 {
lab=Drain2}
N 900 -170 900 -130 {
lab=gnd}
N 720 -170 720 -130 {
lab=gnd}
N 400 -270 400 -230 {
lab=Drain1}
N 490 -270 580 -270 {
lab=Drain1}
N 580 -270 580 -230 {
lab=Drain1}
N 400 -270 490 -270 {
lab=Drain1}
N 580 -170 580 -130 {
lab=gnd}
N 400 -170 400 -130 {
lab=gnd}
N 490 -470 490 -270 {
lab=Drain1}
N 580 -130 720 -130 {
lab=gnd}
N 900 -130 1060 -130 {
lab=gnd}
N 490 -470 680 -200 {
lab=Drain1}
N 620 -200 810 -470 {
lab=Drain2}
N 330 -200 360 -200 {
lab=clk}
N 810 -200 900 -200 {
lab=well}
N 720 -130 900 -130 {
lab=gnd}
N 490 -200 580 -200 {
lab=well}
N 400 -130 580 -130 {
lab=gnd}
N 940 -200 960 -200 {
lab=clk}
N 490 -200 490 -110 {lab=well}
N 650 -110 810 -110 {lab=well}
N 810 -200 810 -110 {lab=well}
N 720 -200 810 -200 {
lab=well}
N 650 -30 650 -10 {lab=gnd}
N 650 -110 650 -90 {lab=well}
N 490 -110 650 -110 {lab=well}
N 390 -200 490 -200 {lab=well}
N 1190 -400 1190 -370 {lab=gnd}
N 1190 -400 1230 -400 {lab=gnd}
N 1230 -400 1230 -280 {lab=gnd}
N 1190 -280 1230 -280 {lab=gnd}
N 1190 -310 1190 -280 {lab=gnd}
N 1140 -340 1190 -340 {lab=well}
C {iopin.sym} 1060 -130 0 0 {name=p2 lab=gnd}
C {ipin.sym} 330 -200 0 0 {name=p6 lab=clk}
C {sg13g2_pr/sg13_lv_nmos.sym} 600 -200 0 1 {name=M6
l=0.200u
w=4.0u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 380 -200 0 0 {name=M10
l=0.200u
w=4.0u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 920 -200 0 1 {name=M7
l=0.200u
w=4.0u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 700 -200 0 0 {name=M8
l=0.200u
w=4.0u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {lab_pin.sym} 960 -200 2 0 {name=p11 sig_type=std_logic lab=clk}
C {iopin.sym} 490 -470 2 0 {name=p1 lab=Drain1}
C {iopin.sym} 810 -470 0 0 {name=p7 lab=Drain2}
C {sg13g2_pr/ptap1.sym} 650 -60 2 0 {name=R2
model=ptap1
spiceprefix=X
w=0.78e-6
l=0.78e-6
}
C {lab_pin.sym} 650 -10 2 0 {name=p3 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 810 -110 2 0 {name=p4 sig_type=std_logic lab=well}
C {sg13g2_pr/sg13_lv_nmos.sym} 1210 -340 0 1 {name=M2
l=0.200u
w=4.0u
ng=1
m=4
model=sg13_lv_nmos
spiceprefix=X
}
C {lab_pin.sym} 1140 -340 0 0 {name=p8 sig_type=std_logic lab=well
m=4}
C {lab_pin.sym} 1190 -400 0 0 {name=p10 sig_type=std_logic lab=gnd
m=4}

1
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Test

0
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/input_pair_cm.nodes → modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/DIFF_COMPARATOR.nodes
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0
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/input_pair_cm.sim → modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/DIFF_COMPARATOR.sim
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124
modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/pex_output/DIFF_COMPARATOR__DIFF_COMPARATOR/magic_RC/DIFF_COMPARATOR.ext Normal file
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timestamp 0
version 8.3
tech ihp-sg13g2
style ngspice()
scale 1000 1 0.5
resistclasses 3000000 67000 110 88 88 88 88 18 11
parameters sg13_lv_nmos l=l w=w a1=as p1=ps a2=ad p2=pd
parameters sg13_lv_pmos l=l w=w a1=as p1=ps a2=ad p2=pd
port "vbias" 4 2148 -579 2236 -495 m3
port "clk" 8 1620 -950 1654 -915 m2
port "out+" 7 6037 2710 6063 2738 m2
port "out-" 6 -1819 2721 -1793 2749 m2
port "V+" 2 979 6959 1061 7055 m3
port "V-" 3 3313 6717 3395 6813 m3
port "vdd" 10 127 335 275 572 m6
port "gnd" 9 -513 -440 -293 -73 m7
node "vbias" 7 2834.31 2148 -579 m3 0 0 0 0 54512 3184 61712 2244 605098 3622 0 0 0 0 0 0 0 0
node "a_1752_817#" 16 442.661 1752 817 pdif 0 0 0 0 315568 9996 275888 7644 509688 8744 0 0 0 0 0 0 0 0
node "clk" 14 7896.06 1620 -950 m2 0 0 0 0 853640 15708 236152 8628 0 0 0 0 0 0 0 0 0 0
node "out+" 5 2361.94 6037 2710 m2 0 0 0 0 291396 5776 930084 9364 0 0 0 0 0 0 0 0 0 0
node "out-" 5 2358.75 -1819 2721 m2 0 0 0 0 291396 5776 930084 9364 0 0 0 0 0 0 0 0 0 0
node "a_944_1911#" 25 4286.17 944 1911 p 0 0 0 0 213640 9556 229760 8018 848474 15962 269080 4124 0 0 0 0 0 0
node "V+" 10 3912.6 979 6959 m3 0 0 0 0 335280 7822 56404 2350 515268 8328 0 0 0 0 0 0 0 0
node "a_687_2445#" 24 4012.69 687 2445 p 0 0 0 0 213640 9556 490160 11738 848614 15964 0 0 0 0 0 0 0 0
node "V-" 10 3931.19 3313 6717 m3 0 0 0 0 312654 7152 96568 3908 523040 8334 0 0 0 0 0 0 0 0
node "a_1245_3300#" 64 1432.03 1245 3300 pdif 0 0 0 0 646952 33468 462832 13040 1797472 26104 193480 3044 0 0 0 0 0 0
node "w_805_2869#" 1242572 5.18828 805 2869 pw 182658 17438 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "vdd" 58 17973.9 127 335 m6 0 0 0 0 2395440 52908 883744 19072 642880 13104 642880 13104 1340864 17360 6062752 36968 0 0
substrate "gnd" 0 0 -513 -440 m7 0 0 0 0 2036008 30746 224000 4320 224000 4320 224000 4320 654400 6472 1331200 8256 9608000 48040
cap "w_805_2869#" "out+" 7.86123
cap "out-" "vbias" 0.0904886
cap "a_1245_3300#" "a_944_1911#" 8045.22
cap "a_944_1911#" "a_1752_817#" 55.7997
cap "a_687_2445#" "vbias" 4.05638
cap "V-" "a_1245_3300#" 941.789
cap "a_1245_3300#" "out-" 367.947
cap "out+" "vdd" 1847.73
cap "V+" "out+" 3.75851
cap "w_805_2869#" "vdd" 153.703
cap "w_805_2869#" "V+" 10.369
cap "a_1245_3300#" "a_687_2445#" 11353.4
cap "a_687_2445#" "a_1752_817#" 45.3073
cap "a_944_1911#" "out+" 800.279
cap "w_805_2869#" "a_944_1911#" 4.42903
cap "clk" "vbias" 198.783
cap "V+" "vdd" 4082.05
cap "V-" "out+" 9.67399
cap "w_805_2869#" "V-" 10.604
cap "out+" "out-" 93.2996
cap "w_805_2869#" "out-" 7.86123
cap "a_1245_3300#" "clk" 447.822
cap "clk" "a_1752_817#" 502.499
cap "a_944_1911#" "vdd" 1108.62
cap "a_687_2445#" "out+" 692.864
cap "V+" "a_944_1911#" 1081.78
cap "w_805_2869#" "a_687_2445#" 3.06666
cap "V-" "vdd" 4061.21
cap "V+" "V-" 1610.45
cap "a_1245_3300#" "vbias" 2.78546
cap "out-" "vdd" 1843.04
cap "V+" "out-" 7.34235
cap "a_1752_817#" "vbias" 2289.93
cap "a_687_2445#" "vdd" 1311.56
cap "V+" "a_687_2445#" 130.255
cap "V-" "a_944_1911#" 469.011
cap "a_1245_3300#" "a_1752_817#" 3765.33
cap "clk" "out+" 16.9002
cap "a_944_1911#" "out-" 611.611
cap "a_687_2445#" "a_944_1911#" 2249.36
cap "V-" "out-" 3.46102
cap "out+" "vbias" 0.0904886
cap "V-" "a_687_2445#" 785.268
cap "clk" "vdd" 2988.42
cap "a_687_2445#" "out-" 894.529
cap "a_1245_3300#" "out+" 369.238
cap "w_805_2869#" "a_1245_3300#" 12.1813
cap "vdd" "vbias" 2839.64
cap "clk" "a_944_1911#" 247.428
cap "a_1245_3300#" "vdd" 2550.93
cap "V+" "a_1245_3300#" 765.727
cap "clk" "out-" 17.6324
cap "a_1752_817#" "vdd" 7111.46
cap "a_944_1911#" "vbias" 3.01856
cap "clk" "a_687_2445#" 238.332
device msubckt sg13_lv_nmos 3710 1075 3711 1076 l=40 w=800 "gnd" "gnd" 80 0 "gnd" 0 0 "gnd" 1600 30400,876
device msubckt sg13_lv_nmos 3594 1075 3595 1076 l=40 w=800 "gnd" "clk" 80 0 "a_944_1911#" 800 57600,944 "gnd" 800 30400,876
device msubckt sg13_lv_nmos 3410 1075 3411 1076 l=40 w=800 "gnd" "a_687_2445#" 80 0 "gnd" 800 30400,876 "a_944_1911#" 800 57600,944
device msubckt sg13_lv_nmos 3294 1075 3295 1076 l=40 w=800 "gnd" "gnd" 80 0 "gnd" 0 0 "gnd" 1600 54400,1736
device msubckt sg13_lv_pmos 1752 885 1753 886 l=60 w=900 "vdd" "vbias" 120 0 "a_1752_817#" 900 61200,1936 "vdd" 900 34200,976
device msubckt sg13_lv_pmos 1752 1021 1753 1022 l=60 w=900 "vdd" "vbias" 120 0 "vdd" 900 34200,976 "a_1752_817#" 900 34200,976
device msubckt sg13_lv_pmos 1752 1157 1753 1158 l=60 w=900 "vdd" "vbias" 120 0 "a_1752_817#" 900 34200,976 "vdd" 900 34200,976
device msubckt sg13_lv_pmos 1752 1293 1753 1294 l=60 w=900 "vdd" "vbias" 120 0 "vdd" 900 34200,976 "a_1752_817#" 900 61200,1936
device msubckt sg13_lv_pmos 1752 1623 1753 1624 l=60 w=900 "vdd" "clk" 120 0 "a_1245_3300#" 900 61200,1936 "a_1752_817#" 900 34200,976
device msubckt sg13_lv_pmos 1752 1759 1753 1760 l=60 w=900 "vdd" "clk" 120 0 "a_1752_817#" 900 34200,976 "a_1245_3300#" 900 34200,976
device msubckt sg13_lv_pmos 1752 1895 1753 1896 l=60 w=900 "vdd" "clk" 120 0 "a_1245_3300#" 900 34200,976 "a_1752_817#" 900 34200,976
device msubckt sg13_lv_pmos 1752 2031 1753 2032 l=60 w=900 "vdd" "clk" 120 0 "a_1752_817#" 900 34200,976 "a_1245_3300#" 900 61200,1936
device msubckt sg13_lv_nmos 1070 1075 1071 1076 l=40 w=800 "gnd" "gnd" 80 0 "gnd" 0 0 "gnd" 1600 30400,876
device msubckt sg13_lv_nmos 954 1075 955 1076 l=40 w=800 "gnd" "a_944_1911#" 80 0 "a_687_2445#" 800 57600,944 "gnd" 800 30400,876
device msubckt sg13_lv_nmos 770 1075 771 1076 l=40 w=800 "gnd" "clk" 80 0 "gnd" 800 30400,876 "a_687_2445#" 800 57600,944
device msubckt sg13_lv_nmos 654 1075 655 1076 l=40 w=800 "gnd" "gnd" 80 0 "gnd" 0 0 "gnd" 1600 54400,1736
device msubckt sg13_lv_nmos 3281 2445 3282 2446 l=40 w=400 "gnd" "a_944_1911#" 80 0 "out+" 400 27200,936 "gnd" 400 15200,476
device msubckt sg13_lv_pmos 2309 2445 2310 2446 l=40 w=800 "vdd" "a_944_1911#" 80 0 "out+" 800 54400,1736 "vdd" 800 30400,876
device msubckt sg13_lv_pmos 1295 2445 1296 2446 l=40 w=800 "vdd" "a_687_2445#" 80 0 "out-" 800 54400,1736 "vdd" 800 30400,876
device msubckt sg13_lv_nmos 3281 2561 3282 2562 l=40 w=400 "gnd" "a_944_1911#" 80 0 "gnd" 400 15200,476 "out+" 400 27200,936
device msubckt sg13_lv_nmos 723 2445 724 2446 l=40 w=400 "gnd" "a_687_2445#" 80 0 "out-" 400 27200,936 "gnd" 400 15200,476
device msubckt sg13_lv_pmos 2309 2561 2310 2562 l=40 w=800 "vdd" "a_944_1911#" 80 0 "vdd" 800 30400,876 "out+" 800 54400,1736
device msubckt sg13_lv_pmos 1295 2561 1296 2562 l=40 w=800 "vdd" "a_687_2445#" 80 0 "vdd" 800 30400,876 "out-" 800 54400,1736
device msubckt sg13_lv_nmos 723 2561 724 2562 l=40 w=400 "gnd" "a_687_2445#" 80 0 "gnd" 400 15200,476 "out-" 400 27200,936
device msubckt sg13_lv_pmos 2357 3367 2358 3368 l=40 w=800 "vdd" "V-" 80 0 "a_1245_3300#" 800 54400,1736 "a_687_2445#" 800 30400,876
device msubckt sg13_lv_pmos 2357 3483 2358 3484 l=40 w=800 "vdd" "V-" 80 0 "a_687_2445#" 800 30400,876 "a_1245_3300#" 800 54400,1736
device msubckt sg13_lv_pmos 1245 3368 1246 3369 l=40 w=800 "vdd" "V+" 80 0 "a_1245_3300#" 800 54400,1736 "a_944_1911#" 800 30400,876
device msubckt sg13_lv_pmos 1245 3484 1246 3485 l=40 w=800 "vdd" "V+" 80 0 "a_944_1911#" 800 30400,876 "a_1245_3300#" 800 54400,1736
device msubckt sg13_lv_pmos 2357 3838 2358 3839 l=40 w=800 "vdd" "V+" 80 0 "a_1245_3300#" 800 54400,1736 "a_944_1911#" 800 30400,876
device msubckt sg13_lv_pmos 2357 3954 2358 3955 l=40 w=800 "vdd" "V+" 80 0 "a_944_1911#" 800 30400,876 "a_1245_3300#" 800 54400,1736
device msubckt sg13_lv_pmos 1245 3839 1246 3840 l=40 w=800 "vdd" "V-" 80 0 "a_1245_3300#" 800 54400,1736 "a_687_2445#" 800 30400,876
device msubckt sg13_lv_pmos 1245 3955 1246 3956 l=40 w=800 "vdd" "V-" 80 0 "a_687_2445#" 800 30400,876 "a_1245_3300#" 800 54400,1736
device msubckt sg13_lv_pmos 2357 4309 2358 4310 l=40 w=800 "vdd" "V-" 80 0 "a_1245_3300#" 800 54400,1736 "a_687_2445#" 800 30400,876
device msubckt sg13_lv_pmos 2357 4425 2358 4426 l=40 w=800 "vdd" "V-" 80 0 "a_687_2445#" 800 30400,876 "a_1245_3300#" 800 54400,1736
device msubckt sg13_lv_pmos 1245 4310 1246 4311 l=40 w=800 "vdd" "V+" 80 0 "a_1245_3300#" 800 54400,1736 "a_944_1911#" 800 30400,876
device msubckt sg13_lv_pmos 1245 4426 1246 4427 l=40 w=800 "vdd" "V+" 80 0 "a_944_1911#" 800 30400,876 "a_1245_3300#" 800 54400,1736
device msubckt sg13_lv_pmos 2357 4780 2358 4781 l=40 w=800 "vdd" "V+" 80 0 "a_1245_3300#" 800 54400,1736 "a_944_1911#" 800 30400,876
device msubckt sg13_lv_pmos 2357 4896 2358 4897 l=40 w=800 "vdd" "V+" 80 0 "a_944_1911#" 800 30400,876 "a_1245_3300#" 800 54400,1736
device msubckt sg13_lv_pmos 1245 4781 1246 4782 l=40 w=800 "vdd" "V-" 80 0 "a_1245_3300#" 800 54400,1736 "a_687_2445#" 800 30400,876
device msubckt sg13_lv_pmos 1245 4897 1246 4898 l=40 w=800 "vdd" "V-" 80 0 "a_687_2445#" 800 30400,876 "a_1245_3300#" 800 54400,1736

1362
modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/pex_output/DIFF_COMPARATOR__DIFF_COMPARATOR/magic_RC/DIFF_COMPARATOR.res.ext Normal file
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27
modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/pex_output/DIFF_COMPARATOR__DIFF_COMPARATOR/magic_RC/DIFF_COMPARATOR_MAGIC_RC_Script.tcl Normal file
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@ -0,0 +1,27 @@
# Generated by kpex 0.2.7
crashbackups stop
drc off
gds read /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/layout/DIFF_COMPARATOR.gds
load DIFF_COMPARATOR
select top cell
flatten DIFF_COMPARATOR_flat
load DIFF_COMPARATOR_flat
cellname delete DIFF_COMPARATOR -noprompt
cellname rename DIFF_COMPARATOR_flat DIFF_COMPARATOR
select top cell
extract path /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/pex_output/DIFF_COMPARATOR__DIFF_COMPARATOR/magic_RC
extract do resistance
extract all
ext2sim labels on
ext2sim
extresist tolerance 1
extresist all
ext2spice short resistor
ext2spice merge conservative
ext2spice cthresh 0.02
ext2spice rthresh 50
ext2spice extresist on
ext2spice subcircuits top on
ext2spice format ngspice
ext2spice -p /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/pex_output/DIFF_COMPARATOR__DIFF_COMPARATOR/magic_RC -o /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/pex_output/DIFF_COMPARATOR__DIFF_COMPARATOR/magic_RC/DIFF_COMPARATOR.pex.spice
quit -noprompt

BIN
modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/pex_output/DIFF_COMPARATOR__DIFF_COMPARATOR/magic_RC/DIFF_COMPARATOR_MAGIC_report.rdb.gz Normal file
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74
modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/python/insert_netlist_to_sym.py Normal file
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@ -0,0 +1,74 @@
import sys
import os
def extract_netlist_and_topcell(spice_path):
with open(spice_path, 'r') as f:
lines = f.readlines()
netlist = []
topcell = None
inside_subckt = False
for line in lines:
if line.strip().startswith(".subckt"):
parts = line.strip().split()
if len(parts) > 1:
topcell = parts[1]
inside_subckt = True
if inside_subckt:
netlist.append(line.rstrip())
if line.strip().startswith(".ends"):
break
if not topcell:
raise ValueError("Topcell name not found in SPICE file.")
return topcell, "\n".join(netlist)
def modify_sym_file(sym_path, output_dir, topcell, netlist):
with open(sym_path, 'r') as f:
sym_lines = f.readlines()
new_sym_lines = []
inserted = False
for line in sym_lines:
if line.strip().startswith("K {type=subcircuit"):
new_sym_lines.append(line)
continue
elif line.strip().startswith("template=") and not inserted:
new_template = (
f'template="name=x1\n'
f'schematic={topcell}\n'
f'spice_sym_def=\n'
f'\\\\"\n'
f'{netlist}\n'
f'\\\\"\n'
f'"'
)
new_sym_lines.append(new_template + "\n")
inserted = True
else:
new_sym_lines.append(line)
filename = os.path.basename(sym_path)
out_path = os.path.join(output_dir, filename)
os.makedirs(output_dir, exist_ok=True)
with open(out_path, 'w') as f:
f.writelines(new_sym_lines)
print(f"Saved modified .sym to: {out_path}")
if __name__ == "__main__":
if len(sys.argv) != 4:
print("Usage: python insert_netlist_to_sym.py <netlist.spice> <symbol.sym> <output_folder>")
sys.exit(1)
spice_file = sys.argv[1]
sym_file = sys.argv[2]
output_folder = sys.argv[3]
topcell, netlist = extract_netlist_and_topcell(spice_file)
modify_sym_file(sym_file, output_folder, topcell, netlist)

0
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/scripts/insert_pex_subckt.py → modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/python/insert_pex_subckt.py
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75
modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/python/match_subckt_order.py Normal file
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@ -0,0 +1,75 @@
import sys
from pathlib import Path
def get_original_io_order(original_netlist_path):
io_pins = []
with open(original_netlist_path, "r") as f:
for line in f:
stripped = line.strip()
if not stripped or stripped.startswith("*"):
continue
if stripped.lower().startswith(".subckt"):
tokens = stripped.split()
if len(tokens) >= 3:
print(f"[INFO] Found .subckt in original: {stripped}")
io_pins = tokens[2:]
break
if not io_pins:
raise ValueError(f"Could not find IO pins in original schematic: {original_netlist_path}")
return io_pins
def reorder_pex_subckt(pex_path, correct_order):
with open(pex_path, "r") as f:
lines = f.readlines()
new_lines = []
subckt_found = False
for line in lines:
stripped = line.strip()
if stripped.lower().startswith(".subckt") and not subckt_found:
tokens = stripped.split()
subckt_name = tokens[1]
ports = tokens[2:]
# Case-insensitive set comparison
ports_lower = [p.lower() for p in ports]
correct_lower = [p.lower() for p in correct_order]
if set(ports_lower) != set(correct_lower):
print("[ERROR] Port name mismatch!")
print("[DEBUG] PEX ports :", ports)
print("[DEBUG] Schematic IOs:", correct_order)
raise ValueError("Port names in PEX netlist don't match original IO pins")
# Map from lower-case pin name to original-cased PEX name
port_map = {p.lower(): p for p in ports}
reordered_ports = [port_map[p.lower()] for p in correct_order]
reordered_line = f".subckt {subckt_name}_pex {' '.join(reordered_ports)}\n"
new_lines.append(reordered_line)
subckt_found = True
else:
new_lines.append(line)
with open(pex_path, "w") as f:
f.writelines(new_lines)
print(f"[INFO] Rewrote subckt line in {pex_path}")
if __name__ == "__main__":
if len(sys.argv) != 3:
print("Usage: python match_subckt_order.py <pex_spice_path> <original_schematic_spice_path>")
sys.exit(1)
pex_spice = Path(sys.argv[1])
original_schematic = Path(sys.argv[2])
print(f"[INFO] Found extracted spice file: {pex_spice}")
print(f"[INFO] Reordering subcircuit pins to match original schematic...")
io_order = get_original_io_order(original_schematic)
reorder_pex_subckt(pex_spice, io_order)

0
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/scripts/xschem_rc.py → modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/python/xschem_rc.py
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65
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/run_kpex.sh → modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/run_kpex.sh
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@ -13,31 +13,21 @@ PYTHON_ENV="$HOME/misc/klayout_pex/bin/activate"
KPEX_MAGIC_EXE="$HOME/.local/bin/magic"
# Example: /usr/local/bin/magic or ~/.local/bin/magic
# Cell and schematic names (do NOT include file extensions)
CELL_NAME="inverter" # The name of your top cell / device under test (DUT)
TESTBENCH_NAME="inverter_tb" # Name of your testbench schematic (without extension)
#Path to symbol
SYM_DIR="../xschem_pre_layout/schematic/DIFF_COMPARATOR.sym" # Asuming you have a symbol for the DUT
# Paths relative to this script or absolute paths
SPICE_DIR="../simulations" # Directory containing netlist/spice files for testbench
LAYOUT_DIR="../layout" # Directory containing layout files (.gds etc.)
# Important: Path to your PDK root directory must be set externally in env variable PDK_ROOT
LAYOUT_DIR="../layout/DIFF_COMPARATOR.gds" # Path to the GDS file
# Important: Path to your PDK root directory must be set externally in env variable PDK_ROOT, otherwise give absolute path
PDK_NAME="ihp_sg13g2" # Your PDK name (must match PDK_ROOT contents)
MAGICRC="$PDK_ROOT/$PDK/libs.tech/magic/ihp-sg13g2.magicrc"
# The magicrc file for your PDK, used during extraction
MAGICRC="$PDK_ROOT/$PDK/libs.tech/magic/ihp-sg13g2.magicrc" # The magicrc file for your PDK, used during extraction
# Path to your testbench schematic file (relative or absolute)
# You can override this here if your schematic is located elsewhere
TESTBENCH_PATH="../${TESTBENCH_NAME}.sch"
SCHEMATIC="../layout/lvs_netlist/DIFF_COMPARATOR.spice" # Spicefile of the comparator from Schematic or LVS (Used for pex to perform LVS and script to organize IO)
##############################################################################################################################################################
# ⛔ DO NOT TOUCH BELOW THIS LINE ⛔ Unless you see clear issue with your setup :) #
##############################################################################################################################################################
# Derived paths based on above variables
LAYOUT_GDS="${LAYOUT_DIR}/${CELL_NAME}.gds"
REFERENCE_SPICE="${SPICE_DIR}/${TESTBENCH_NAME}.spice"
# Check if required files exist before proceeding
if [[ ! -f "$PYTHON_ENV" ]]; then
@ -50,20 +40,11 @@ if [[ ! -x "$KPEX_MAGIC_EXE" ]]; then
exit 1
fi
if [[ ! -f "$LAYOUT_GDS" ]]; then
echo "[ERROR] Layout GDS file not found: $LAYOUT_GDS"
if [[ ! -f "$LAYOUT_DIR" ]]; then
echo "[ERROR] Layout GDS file not found: $LAYOUT_DIR"
exit 1
fi
if [[ ! -f "$REFERENCE_SPICE" ]]; then
echo "[ERROR] Reference spice file not found: $REFERENCE_SPICE"
exit 1
fi
if [[ ! -f "$TESTBENCH_PATH" ]]; then
echo "[ERROR] Testbench schematic file not found: $TESTBENCH_PATH"
exit 1
fi
if [[ ! -f "$MAGICRC" ]]; then
echo "[ERROR] Magicrc file for PDK not found: $MAGICRC"
@ -81,9 +62,8 @@ echo "[INFO] Running parasitic extraction with KPEX..."
kpex \
--pdk "$PDK_NAME" \
--magic \
--gds "$LAYOUT_GDS" \
--schematic "$REFERENCE_SPICE" \
--cell "$CELL_NAME" \
--schematic "$SCHEMATIC"\
--gds "$LAYOUT_DIR" \
--magicrc "$MAGICRC" \
--magic_mode RC \
--magic_cthresh 0.02 \
@ -92,11 +72,9 @@ kpex \
--magic_merge conservative \
--out_dir ./pex_output
# Create working directory for schematic updates if not exists
mkdir -p xschem
# Find the generated spice file (assuming only one)
spice_location=$(find ./pex_output -type f -name "*.spice" | head -n 1)
spice_location=$(find ./pex_output -type f -name "*.spice" ! -name "*_dummy_schematic.spice" | head -n 1)
if [[ -z "$spice_location" ]]; then
echo "[ERROR] No .spice file found in pex_output directory"
@ -107,20 +85,15 @@ echo "[INFO] Found extracted spice file: $spice_location"
# Run Python script to fix port ordering in the extracted netlist
echo "[INFO] Reordering subcircuit pins to match original schematic..."
python3 scripts/match_subckt_order.py "$spice_location" "$REFERENCE_SPICE"
echo "$spice_location"
echo "$SCHEMATIC"
# Enter schematic directory
cd xschem || { echo "[ERROR] Failed to enter xschem directory"; exit 1; }
python3 python/match_subckt_order.py "$spice_location" "$SCHEMATIC"
# Run python script to update schematic with PEX subcircuit
echo "[INFO] Updating schematic with PEX subcircuit..."
python3 ../scripts/insert_pex_subckt.py "../$TESTBENCH_PATH" "../$spice_location" # remark this is relatives path native to my setup
# Generate xschemrc file pointing to schematic and symbol folders
# Adjust this path if your schematic/symbols are elsewhere
XSCHEM_PATH="../../" # relative to current 'xschem' folder (points to symbol for the DUT)
echo "[INFO] Generating xschemrc file..."
python3 ../scripts/xschem_rc.py "$XSCHEM_PATH"
echo "[INFO] Creating DUT symbol with pex netlist"
python3 python/insert_netlist_to_sym.py "$spice_location" "$SYM_DIR" xschem_pex_symbol
echo "[✅ DONE] Modified schematic generated and saved in: $(pwd)/"
cd xschem_pex_symbol
echo "[✅ DONE] Modified symbol, including pex netlist generated and saved in: $(pwd)/"

947
modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/xschem_pex_symbol/DIFF_COMPARATOR.sym Normal file
View File

@ -0,0 +1,947 @@
v {xschem version=3.4.5 file_version=1.2
}
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1
schematic=DIFF_COMPARATOR_pex
spice_sym_def=
\\"
.subckt DIFF_COMPARATOR_pex vdd gnd V+ V- clk out- out+ vbias
X0 a_687_2445# V- a_1245_3300# vdd sg13_lv_pmos ad=0.76p pd=4.38u as=1.36p ps=8.68u w=4u l=0.2u M=8
X1 a_944_1911# V+ a_1245_3300# vdd sg13_lv_pmos ad=0.76p pd=4.38u as=1.36p ps=8.68u w=4u l=0.2u M=8
X2 a_1752_817# vbias vdd vdd sg13_lv_pmos ad=1.53p pd=9.68u as=0.855p ps=4.88u w=4.5u l=0.3u M=4
X3 gnd gnd gnd gnd sg13_lv_nmos ad=1.36p pd=8.68u as=50.9002p ps=0.15373m w=4u l=0.2u M=4
X4 vdd a_944_1911# out+ vdd sg13_lv_pmos ad=0.76p pd=4.38u as=1.36p ps=8.68u w=4u l=0.2u M=2
X5 a_944_1911# a_687_2445# gnd gnd sg13_lv_nmos ad=1.44p pd=4.72u as=0.76p ps=4.38u w=4u l=0.2u
X6 a_687_2445# clk gnd gnd sg13_lv_nmos ad=1.44p pd=4.72u as=0.76p ps=4.38u w=4u l=0.2u
X7 gnd a_944_1911# a_687_2445# gnd sg13_lv_nmos ad=0.76p pd=4.38u as=1.44p ps=4.72u w=4u l=0.2u
X8 out- a_687_2445# gnd gnd sg13_lv_nmos ad=0.68p pd=4.68u as=0.38p ps=2.38u w=2u l=0.2u M=2
X9 gnd clk a_944_1911# gnd sg13_lv_nmos ad=0.76p pd=4.38u as=1.44p ps=4.72u w=4u l=0.2u
X10 out- a_687_2445# vdd vdd sg13_lv_pmos ad=1.36p pd=8.68u as=0.76p ps=4.38u w=4u l=0.2u M=2
X11 out+ a_944_1911# gnd gnd sg13_lv_nmos ad=0.68p pd=4.68u as=0.38p ps=2.38u w=2u l=0.2u M=2
X12 a_1245_3300# clk a_1752_817# vdd sg13_lv_pmos ad=1.53p pd=9.68u as=0.855p ps=4.88u w=4.5u l=0.3u M=4
C0 a_1752_817# a_1245_3300# 3.76533f
C1 a_944_1911# a_1245_3300# 8.04522f
C2 out- out+ 0.0933f
C3 clk a_1245_3300# 0.44782f
C4 w_805_2869# vdd 0.1537f
C5 V+ a_1245_3300# 0.76573f
C6 V- a_1245_3300# 0.94179f
C7 a_1245_3300# vdd 2.55093f
C8 a_944_1911# a_1752_817# 0.0558f
C9 a_1245_3300# a_687_2445# 11.3534f
C10 a_1752_817# vbias 2.28993f
C11 a_1752_817# clk 0.5025f
C12 a_944_1911# clk 0.24743f
C13 V+ a_944_1911# 1.08178f
C14 V- a_944_1911# 0.46901f
C15 a_1245_3300# out+ 0.36924f
C16 clk vbias 0.19878f
C17 a_1245_3300# out- 0.36795f
C18 a_1752_817# vdd 7.11146f
C19 a_1752_817# a_687_2445# 0.04531f
C20 a_944_1911# vdd 1.10862f
C21 a_944_1911# a_687_2445# 2.24936f
C22 vbias vdd 2.83964f
C23 clk vdd 2.98842f
C24 V- V+ 1.61045f
C25 clk a_687_2445# 0.23833f
C26 V+ vdd 4.08205f
C27 V- vdd 4.06121f
C28 V+ a_687_2445# 0.13025f
C29 V- a_687_2445# 0.78527f
C30 a_944_1911# out+ 0.80028f
C31 a_944_1911# out- 0.61161f
C32 a_687_2445# vdd 1.31156f
C33 vdd out+ 1.84773f
C34 a_687_2445# out+ 0.69286f
C35 vdd out- 1.84304f
C36 a_687_2445# out- 0.89453f
R0 V+.n6 V+.n0 17.1875
R1 V+.n6 V+.n5 16.5321
R2 V+.n2 V+.n1 15.8046
R3 V+.n4 V+.n3 9.60223
R4 V+.n4 V+.n1 8.28871
R5 V+.n3 V+.n0 8.28871
R6 V+.n5 V+.n4 7.51146
R7 V+.n3 V+.n2 7.51146
R8 V+ V+.n6 1.77098
R9 V-.n6 V-.n0 17.1792
R10 V-.n3 V-.n0 17.1129
R11 V-.n4 V-.n1 17.1083
R12 V-.n6 V-.n5 16.5321
R13 V-.n2 V-.n1 15.8156
R14 V-.n5 V-.n4 7.51146
R15 V-.n3 V-.n2 7.51146
R16 V- V-.n6 1.57783
R17 V-.n4 V-.n3 0.792909
R18 vbias vbias.n0 6.1153
R19 out-.n17 out-.n1 17.0005
R20 out-.n22 out-.n1 17.0005
R21 out-.n13 out-.n1 17.0005
R22 out-.n35 out-.n7 17.0005
R23 out-.n35 out-.n6 17.0005
R24 out-.n35 out-.n8 17.0005
R25 out-.n42 out-.n41 9.04081
R26 out-.n12 out-.n10 9.03703
R27 out-.n24 out-.n23 9.0005
R28 out-.n21 out-.n20 9.0005
R29 out-.n16 out-.n3 9.0005
R30 out-.n40 out-.n39 9.0005
R31 out-.n31 out-.n30 9.0005
R32 out-.n28 out-.n27 9.0005
R33 out-.n45 out-.n43 9.0005
R34 out-.n46 out-.n43 9.0005
R35 out-.n44 out-.n43 9.0005
R36 out-.n51 out-.n43 9.0005
R37 out-.n52 out-.n45 9.0005
R38 out-.n52 out-.n46 9.0005
R39 out-.n52 out-.n44 9.0005
R40 out-.n52 out-.n51 9.0005
R41 out-.n36 out-.n35 8.501
R42 out-.n12 out-.n1 8.50006
R43 out-.n35 out-.n5 8.49923
R44 out-.n50 out-.n49 8.49864
R45 out-.n49 out-.n47 8.49864
R46 out-.n41 out-.n1 8.49628
R47 out-.n49 out-.n48 8.49096
R48 out-.n35 out-.n4 8.49007
R49 out-.n35 out-.n34 8.49007
R50 out-.n2 out-.n1 8.46606
R51 out-.n29 out-.n1 8.46606
R52 out-.n10 out-.n5 4.51473
R53 out-.n36 out-.n0 4.51194
R54 out-.n38 out-.n37 4.5005
R55 out-.n19 out-.n18 4.5005
R56 out-.n15 out-.n14 4.5005
R57 out-.n26 out-.n25 4.5005
R58 out-.n11 out-.n9 4.5005
R59 out-.n33 out-.n32 4.5005
R60 out- out-.n53 1.4685
R61 out-.n30 out-.n12 0.146886
R62 out-.n41 out-.n40 0.143078
R63 out-.n17 out-.n16 0.137052
R64 out-.n28 out-.n13 0.129466
R65 out-.n53 out-.n42 0.126844
R66 out-.n40 out-.n2 0.108815
R67 out-.n30 out-.n29 0.101229
R68 out-.n22 out-.n21 0.0953276
R69 out-.n23 out-.n22 0.0877414
R70 out-.n29 out-.n28 0.0822633
R71 out-.n16 out-.n2 0.0746771
R72 out-.n23 out-.n13 0.0536034
R73 out-.n37 out-.n36 0.0468193
R74 out-.n21 out-.n17 0.0460172
R75 out-.n50 out-.n44 0.0453402
R76 out-.n47 out-.n46 0.0453402
R77 out-.n33 out-.n5 0.0450428
R78 out-.n9 out-.n8 0.043672
R79 out-.n18 out-.n7 0.0401237
R80 out-.n34 out-.n33 0.0352729
R81 out-.n37 out-.n4 0.0317246
R82 out-.n25 out-.n6 0.0306613
R83 out-.n48 out-.n44 0.0293633
R84 out-.n48 out-.n46 0.0293633
R85 out-.n14 out-.n6 0.0271129
R86 out-.n18 out-.n4 0.0269934
R87 out-.n34 out-.n9 0.023445
R88 out-.n32 out-.n10 0.019037
R89 out-.n31 out-.n11 0.019037
R90 out-.n27 out-.n26 0.019037
R91 out-.n24 out-.n15 0.019037
R92 out-.n20 out-.n19 0.019037
R93 out-.n38 out-.n3 0.019037
R94 out-.n39 out-.n0 0.019037
R95 out-.n14 out-.n7 0.0176505
R96 out-.n25 out-.n8 0.0141022
R97 out-.n51 out-.n50 0.0134159
R98 out-.n47 out-.n45 0.0134159
R99 out-.n53 out-.n43 0.0127081
R100 out-.n53 out-.n52 0.0127081
R101 out-.n32 out-.n31 0.00151852
R102 out-.n27 out-.n11 0.00151852
R103 out-.n26 out-.n24 0.00151852
R104 out-.n20 out-.n15 0.00151852
R105 out-.n19 out-.n3 0.00151852
R106 out-.n39 out-.n38 0.00151852
R107 out-.n42 out-.n0 0.00151852
R108 out+.n40 out+.n5 17.0005
R109 out+.n40 out+.n2 17.0005
R110 out+.n40 out+.n6 17.0005
R111 out+.n34 out+.n33 17.0005
R112 out+.n33 out+.n14 17.0005
R113 out+.n33 out+.n17 17.0005
R114 out+.n29 out+.n4 9.04081
R115 out+.n42 out+.n41 9.03703
R116 out+.n10 out+.n9 9.0005
R117 out+.n21 out+.n20 9.0005
R118 out+.n25 out+.n24 9.0005
R119 out+.n28 out+.n27 9.0005
R120 out+.n7 out+.n1 9.0005
R121 out+.n38 out+.n37 9.0005
R122 out+.n45 out+.n43 9.0005
R123 out+.n46 out+.n43 9.0005
R124 out+.n44 out+.n43 9.0005
R125 out+.n51 out+.n43 9.0005
R126 out+.n52 out+.n45 9.0005
R127 out+.n52 out+.n46 9.0005
R128 out+.n52 out+.n44 9.0005
R129 out+.n52 out+.n51 9.0005
R130 out+.n33 out+.n16 8.501
R131 out+.n41 out+.n40 8.50006
R132 out+.n33 out+.n13 8.49923
R133 out+.n49 out+.n47 8.49864
R134 out+.n50 out+.n49 8.49864
R135 out+.n40 out+.n4 8.49628
R136 out+.n49 out+.n48 8.49096
R137 out+.n33 out+.n11 8.49007
R138 out+.n33 out+.n32 8.49007
R139 out+.n40 out+.n3 8.46606
R140 out+.n40 out+.n39 8.46606
R141 out+.n29 out+.n13 4.51392
R142 out+.n16 out+.n0 4.51194
R143 out+.n31 out+.n30 4.5005
R144 out+.n26 out+.n18 4.5005
R145 out+.n23 out+.n22 4.5005
R146 out+.n19 out+.n12 4.5005
R147 out+.n36 out+.n35 4.5005
R148 out+.n15 out+.n8 4.5005
R149 out+ out+.n53 1.36221
R150 out+.n41 out+.n1 0.146886
R151 out+.n27 out+.n4 0.143078
R152 out+.n24 out+.n5 0.137052
R153 out+.n38 out+.n6 0.129466
R154 out+.n53 out+.n42 0.127659
R155 out+.n27 out+.n3 0.108815
R156 out+.n39 out+.n1 0.101229
R157 out+.n20 out+.n2 0.0953276
R158 out+.n9 out+.n2 0.0877414
R159 out+.n39 out+.n38 0.0822633
R160 out+.n24 out+.n3 0.0746771
R161 out+.n9 out+.n6 0.0536034
R162 out+.n16 out+.n15 0.0468193
R163 out+.n20 out+.n5 0.0460172
R164 out+.n50 out+.n44 0.0453402
R165 out+.n47 out+.n46 0.0453402
R166 out+.n31 out+.n13 0.0450428
R167 out+.n18 out+.n17 0.043672
R168 out+.n35 out+.n34 0.0401237
R169 out+.n32 out+.n31 0.0352729
R170 out+.n15 out+.n11 0.0317246
R171 out+.n22 out+.n14 0.0306613
R172 out+.n48 out+.n44 0.0293633
R173 out+.n48 out+.n46 0.0293633
R174 out+.n14 out+.n12 0.0271129
R175 out+.n35 out+.n11 0.0269934
R176 out+.n32 out+.n18 0.023445
R177 out+.n7 out+.n0 0.0198519
R178 out+.n37 out+.n8 0.0198519
R179 out+.n36 out+.n10 0.0198519
R180 out+.n21 out+.n19 0.0198519
R181 out+.n25 out+.n23 0.0198519
R182 out+.n28 out+.n26 0.0198519
R183 out+.n30 out+.n29 0.0198519
R184 out+.n34 out+.n12 0.0176505
R185 out+.n22 out+.n17 0.0141022
R186 out+.n51 out+.n50 0.0134159
R187 out+.n47 out+.n45 0.0134159
R188 out+.n53 out+.n43 0.0127081
R189 out+.n53 out+.n52 0.0127081
R190 out+.n42 out+.n0 0.000703704
R191 out+.n8 out+.n7 0.000703704
R192 out+.n37 out+.n36 0.000703704
R193 out+.n19 out+.n10 0.000703704
R194 out+.n23 out+.n21 0.000703704
R195 out+.n26 out+.n25 0.000703704
R196 out+.n30 out+.n28 0.000703704
R197 clk.n4 clk.n0 32.251
R198 clk.n3 clk.n2 29.4509
R199 clk.n3 clk.n1 12.2999
R200 clk.n4 clk.n3 2.20443
R201 clk clk.n4 0.574117
R202 vdd.n208 vdd.n190 17.0005
R203 vdd.n208 vdd.n188 17.0005
R204 vdd.n208 vdd.n191 17.0005
R205 vdd.n208 vdd.n186 17.0005
R206 vdd.n208 vdd.n207 17.0005
R207 vdd.n239 vdd.n178 17.0005
R208 vdd.n179 vdd.n178 17.0005
R209 vdd.n232 vdd.n178 17.0005
R210 vdd.n227 vdd.n178 17.0005
R211 vdd.n225 vdd.n178 17.0005
R212 vdd.n210 vdd.n209 9.05964
R213 vdd.n189 vdd.n176 9.05964
R214 vdd.n222 vdd.n183 9.05964
R215 vdd.n242 vdd.n241 9.05964
R216 vdd.n226 vdd.n182 9.0005
R217 vdd.n229 vdd.n228 9.0005
R218 vdd.n231 vdd.n230 9.0005
R219 vdd.n233 vdd.n180 9.0005
R220 vdd.n236 vdd.n235 9.0005
R221 vdd.n238 vdd.n237 9.0005
R222 vdd.n240 vdd.n177 9.0005
R223 vdd.n224 vdd.n223 9.0005
R224 vdd.n206 vdd.n205 9.0005
R225 vdd.n204 vdd.n203 9.0005
R226 vdd.n202 vdd.n201 9.0005
R227 vdd.n200 vdd.n199 9.0005
R228 vdd.n198 vdd.n197 9.0005
R229 vdd.n196 vdd.n195 9.0005
R230 vdd.n194 vdd.n193 9.0005
R231 vdd.n185 vdd.n184 9.0005
R232 vdd.n128 vdd.n127 8.501
R233 vdd.n115 vdd.n89 8.501
R234 vdd.n98 vdd.n97 8.501
R235 vdd.n81 vdd.n80 8.501
R236 vdd.n134 vdd.n69 8.501
R237 vdd.n208 vdd.n189 8.47918
R238 vdd.n208 vdd.n187 8.47918
R239 vdd.n208 vdd.n192 8.47918
R240 vdd.n209 vdd.n208 8.47918
R241 vdd.n241 vdd.n178 8.47918
R242 vdd.n234 vdd.n178 8.47918
R243 vdd.n181 vdd.n178 8.47918
R244 vdd.n183 vdd.n178 8.47918
R245 vdd.n87 vdd.n86 5.66778
R246 vdd.n243 vdd.n176 5.20536
R247 vdd.n221 vdd.n210 5.20536
R248 vdd.n222 vdd.n221 4.6895
R249 vdd.n243 vdd.n242 4.6895
R250 vdd.n245 vdd.n173 4.56174
R251 vdd.n249 vdd.n174 4.56174
R252 vdd.n215 vdd.n211 4.56174
R253 vdd.n219 vdd.n212 4.56174
R254 vdd.n165 vdd.n2 4.56174
R255 vdd.n169 vdd.n3 4.56174
R256 vdd.n11 vdd.n7 4.56174
R257 vdd.n15 vdd.n8 4.56174
R258 vdd.n28 vdd.n25 4.56174
R259 vdd.n32 vdd.n26 4.56174
R260 vdd.n38 vdd.n35 4.56174
R261 vdd.n42 vdd.n36 4.56174
R262 vdd.n48 vdd.n45 4.56174
R263 vdd.n52 vdd.n46 4.56174
R264 vdd.n136 vdd.n66 4.56174
R265 vdd.n140 vdd.n67 4.56174
R266 vdd.n74 vdd.n70 4.56174
R267 vdd.n78 vdd.n71 4.56174
R268 vdd.n100 vdd.n93 4.56174
R269 vdd.n104 vdd.n94 4.56174
R270 vdd.n109 vdd.n90 4.56174
R271 vdd.n113 vdd.n91 4.56174
R272 vdd.n121 vdd.n117 4.56174
R273 vdd.n125 vdd.n118 4.56174
R274 vdd.n145 vdd.n22 4.56174
R275 vdd.n149 vdd.n23 4.56174
R276 vdd.n58 vdd.n55 4.56174
R277 vdd.n62 vdd.n56 4.56174
R278 vdd.n248 vdd.n247 4.5005
R279 vdd.n246 vdd.n175 4.5005
R280 vdd.n218 vdd.n217 4.5005
R281 vdd.n216 vdd.n213 4.5005
R282 vdd.n166 vdd.n4 4.5005
R283 vdd.n168 vdd.n167 4.5005
R284 vdd.n12 vdd.n9 4.5005
R285 vdd.n14 vdd.n13 4.5005
R286 vdd.n29 vdd.n27 4.5005
R287 vdd.n31 vdd.n30 4.5005
R288 vdd.n39 vdd.n37 4.5005
R289 vdd.n41 vdd.n40 4.5005
R290 vdd.n49 vdd.n47 4.5005
R291 vdd.n51 vdd.n50 4.5005
R292 vdd.n137 vdd.n68 4.5005
R293 vdd.n139 vdd.n138 4.5005
R294 vdd.n75 vdd.n72 4.5005
R295 vdd.n77 vdd.n76 4.5005
R296 vdd.n101 vdd.n95 4.5005
R297 vdd.n103 vdd.n102 4.5005
R298 vdd.n110 vdd.n92 4.5005
R299 vdd.n112 vdd.n111 4.5005
R300 vdd.n122 vdd.n119 4.5005
R301 vdd.n124 vdd.n123 4.5005
R302 vdd.n146 vdd.n24 4.5005
R303 vdd.n148 vdd.n147 4.5005
R304 vdd.n59 vdd.n57 4.5005
R305 vdd.n61 vdd.n60 4.5005
R306 vdd.n133 vdd.n132 4.16092
R307 vdd.n116 vdd.n82 4.16066
R308 vdd.n96 vdd.n84 4.16066
R309 vdd.n88 vdd.n83 4.16054
R310 vdd.n154 vdd.n6 4.16048
R311 vdd.n158 vdd.n6 4.16048
R312 vdd.n162 vdd.n6 4.16048
R313 vdd.n131 vdd.n82 2.83383
R314 vdd.n131 vdd.n83 2.83383
R315 vdd.n131 vdd.n84 2.83383
R316 vdd.n132 vdd.n131 2.83383
R317 vdd.n21 vdd.n6 2.7354
R318 vdd.n245 vdd.n244 2.28117
R319 vdd.n244 vdd.n174 2.28117
R320 vdd.n220 vdd.n211 2.28117
R321 vdd.n220 vdd.n219 2.28117
R322 vdd.n165 vdd.n164 2.28117
R323 vdd.n164 vdd.n3 2.28117
R324 vdd.n16 vdd.n7 2.28117
R325 vdd.n16 vdd.n15 2.28117
R326 vdd.n28 vdd.n17 2.28117
R327 vdd.n26 vdd.n17 2.28117
R328 vdd.n38 vdd.n18 2.28117
R329 vdd.n36 vdd.n18 2.28117
R330 vdd.n48 vdd.n19 2.28117
R331 vdd.n46 vdd.n19 2.28117
R332 vdd.n136 vdd.n135 2.28117
R333 vdd.n135 vdd.n67 2.28117
R334 vdd.n79 vdd.n70 2.28117
R335 vdd.n79 vdd.n78 2.28117
R336 vdd.n100 vdd.n99 2.28117
R337 vdd.n99 vdd.n94 2.28117
R338 vdd.n114 vdd.n90 2.28117
R339 vdd.n114 vdd.n113 2.28117
R340 vdd.n126 vdd.n117 2.28117
R341 vdd.n126 vdd.n125 2.28117
R342 vdd.n150 vdd.n22 2.28117
R343 vdd.n150 vdd.n149 2.28117
R344 vdd.n58 vdd.n20 2.28117
R345 vdd.n56 vdd.n20 2.28117
R346 vdd.n250 vdd.n173 2.25769
R347 vdd.n250 vdd.n249 2.25769
R348 vdd.n215 vdd.n214 2.25769
R349 vdd.n214 vdd.n212 2.25769
R350 vdd.n170 vdd.n2 2.25769
R351 vdd.n170 vdd.n169 2.25769
R352 vdd.n11 vdd.n10 2.25769
R353 vdd.n10 vdd.n8 2.25769
R354 vdd.n33 vdd.n25 2.25769
R355 vdd.n33 vdd.n32 2.25769
R356 vdd.n43 vdd.n35 2.25769
R357 vdd.n43 vdd.n42 2.25769
R358 vdd.n53 vdd.n45 2.25769
R359 vdd.n53 vdd.n52 2.25769
R360 vdd.n141 vdd.n66 2.25769
R361 vdd.n141 vdd.n140 2.25769
R362 vdd.n74 vdd.n73 2.25769
R363 vdd.n73 vdd.n71 2.25769
R364 vdd.n105 vdd.n93 2.25769
R365 vdd.n105 vdd.n104 2.25769
R366 vdd.n109 vdd.n108 2.25769
R367 vdd.n108 vdd.n91 2.25769
R368 vdd.n121 vdd.n120 2.25769
R369 vdd.n120 vdd.n118 2.25769
R370 vdd.n145 vdd.n144 2.25769
R371 vdd.n144 vdd.n23 2.25769
R372 vdd.n63 vdd.n55 2.25769
R373 vdd.n63 vdd.n62 2.25769
R374 vdd.n156 vdd.n6 1.99818
R375 vdd.n160 vdd.n6 1.9981
R376 vdd.n244 vdd.n243 1.89937
R377 vdd.n221 vdd.n220 1.89937
R378 vdd.n164 vdd.n163 1.66843
R379 vdd.n161 vdd.n16 1.66843
R380 vdd.n159 vdd.n17 1.66843
R381 vdd.n157 vdd.n18 1.66843
R382 vdd.n155 vdd.n19 1.66843
R383 vdd.n135 vdd.n134 1.66843
R384 vdd.n80 vdd.n79 1.66843
R385 vdd.n99 vdd.n98 1.66843
R386 vdd.n115 vdd.n114 1.66843
R387 vdd.n127 vdd.n126 1.66843
R388 vdd.n151 vdd.n150 1.66843
R389 vdd.n153 vdd.n20 1.66843
R390 vdd.n152 vdd.n151 1.52562
R391 vdd.n153 vdd.n152 1.2834
R392 vdd.n86 vdd.n5 1.27296
R393 vdd.n86 vdd.n85 1.21158
R394 vdd.n64 vdd.n63 1.1005
R395 vdd.n54 vdd.n53 1.1005
R396 vdd.n44 vdd.n43 1.1005
R397 vdd.n34 vdd.n33 1.1005
R398 vdd.n10 vdd.n1 1.1005
R399 vdd.n171 vdd.n170 1.1005
R400 vdd.n144 vdd.n143 1.1005
R401 vdd.n120 vdd.n0 1.1005
R402 vdd.n108 vdd.n107 1.1005
R403 vdd.n106 vdd.n105 1.1005
R404 vdd.n73 vdd.n65 1.1005
R405 vdd.n142 vdd.n141 1.1005
R406 vdd.n214 vdd.n172 1.1005
R407 vdd.n251 vdd.n250 1.1005
R408 vdd.n127 vdd.n85 1.0667
R409 vdd.n163 vdd.n5 0.897218
R410 vdd.n130 vdd.n129 0.740086
R411 vdd.n129 vdd.n85 0.513736
R412 vdd.n6 vdd.n5 0.434488
R413 vdd.n134 vdd.n21 0.405564
R414 vdd.n127 vdd.n116 0.338749
R415 vdd.n163 vdd.n162 0.338361
R416 vdd.n115 vdd.n88 0.332914
R417 vdd.n98 vdd.n96 0.328172
R418 vdd.n159 vdd.n158 0.327784
R419 vdd.n133 vdd.n80 0.322902
R420 vdd.n155 vdd.n154 0.317207
R421 vdd.n161 vdd.n160 0.30387
R422 vdd.n157 vdd.n156 0.29911
R423 vdd.n156 vdd.n155 0.273116
R424 vdd.n154 vdd.n153 0.272784
R425 vdd.n160 vdd.n159 0.268235
R426 vdd.n134 vdd.n133 0.267129
R427 vdd.n158 vdd.n157 0.262207
R428 vdd.n96 vdd.n80 0.261823
R429 vdd.n98 vdd.n88 0.257063
R430 vdd.n162 vdd.n161 0.25163
R431 vdd.n116 vdd.n115 0.251246
R432 vdd.n143 vdd.n64 0.245476
R433 vdd.n172 vdd.n171 0.223305
R434 vdd.n130 vdd.n6 0.187367
R435 vdd.n151 vdd.n21 0.179715
R436 vdd.n252 vdd.n0 0.142854
R437 vdd.n223 vdd.n222 0.0965
R438 vdd.n223 vdd.n182 0.0965
R439 vdd.n229 vdd.n182 0.0965
R440 vdd.n230 vdd.n229 0.0965
R441 vdd.n230 vdd.n180 0.0965
R442 vdd.n236 vdd.n180 0.0965
R443 vdd.n237 vdd.n236 0.0965
R444 vdd.n237 vdd.n177 0.0965
R445 vdd.n242 vdd.n177 0.0965
R446 vdd.n210 vdd.n184 0.0965
R447 vdd.n205 vdd.n184 0.0965
R448 vdd.n205 vdd.n204 0.0965
R449 vdd.n204 vdd.n202 0.0965
R450 vdd.n202 vdd.n200 0.0965
R451 vdd.n200 vdd.n198 0.0965
R452 vdd.n198 vdd.n196 0.0965
R453 vdd.n196 vdd.n194 0.0965
R454 vdd.n194 vdd.n176 0.0965
R455 vdd.n152 vdd.n6 0.0898978
R456 vdd.n203 vdd.n186 0.083
R457 vdd.n197 vdd.n188 0.083
R458 vdd.n228 vdd.n227 0.083
R459 vdd.n235 vdd.n179 0.083
R460 vdd.n252 vdd.n251 0.0809512
R461 vdd.n201 vdd.n192 0.0721377
R462 vdd.n199 vdd.n187 0.0721377
R463 vdd.n231 vdd.n181 0.0721377
R464 vdd.n234 vdd.n233 0.0721377
R465 vdd.n207 vdd.n185 0.0705
R466 vdd.n193 vdd.n190 0.0705
R467 vdd.n225 vdd.n224 0.0705
R468 vdd.n240 vdd.n239 0.0705
R469 vdd.n209 vdd.n185 0.0621377
R470 vdd.n193 vdd.n189 0.0621377
R471 vdd.n224 vdd.n183 0.0621377
R472 vdd.n241 vdd.n240 0.0621377
R473 vdd.n248 vdd.n175 0.0608429
R474 vdd.n247 vdd.n246 0.0608429
R475 vdd.n218 vdd.n213 0.0608429
R476 vdd.n217 vdd.n216 0.0608429
R477 vdd.n168 vdd.n4 0.0608429
R478 vdd.n167 vdd.n166 0.0608429
R479 vdd.n13 vdd.n12 0.0608429
R480 vdd.n14 vdd.n9 0.0608429
R481 vdd.n31 vdd.n27 0.0608429
R482 vdd.n30 vdd.n29 0.0608429
R483 vdd.n41 vdd.n37 0.0608429
R484 vdd.n40 vdd.n39 0.0608429
R485 vdd.n51 vdd.n47 0.0608429
R486 vdd.n50 vdd.n49 0.0608429
R487 vdd.n139 vdd.n68 0.0608429
R488 vdd.n138 vdd.n137 0.0608429
R489 vdd.n76 vdd.n75 0.0608429
R490 vdd.n77 vdd.n72 0.0608429
R491 vdd.n103 vdd.n95 0.0608429
R492 vdd.n102 vdd.n101 0.0608429
R493 vdd.n111 vdd.n110 0.0608429
R494 vdd.n112 vdd.n92 0.0608429
R495 vdd.n123 vdd.n122 0.0608429
R496 vdd.n124 vdd.n119 0.0608429
R497 vdd.n147 vdd.n146 0.0608429
R498 vdd.n148 vdd.n24 0.0608429
R499 vdd.n60 vdd.n59 0.0608429
R500 vdd.n61 vdd.n57 0.0608429
R501 vdd.n201 vdd.n191 0.0605
R502 vdd.n199 vdd.n191 0.0605
R503 vdd.n232 vdd.n231 0.0605
R504 vdd.n233 vdd.n232 0.0605
R505 vdd.n251 vdd.n172 0.0577927
R506 vdd.n207 vdd.n206 0.0505
R507 vdd.n195 vdd.n190 0.0505
R508 vdd.n226 vdd.n225 0.0505
R509 vdd.n239 vdd.n238 0.0505
R510 vdd.n203 vdd.n192 0.0496377
R511 vdd.n197 vdd.n187 0.0496377
R512 vdd.n228 vdd.n181 0.0496377
R513 vdd.n235 vdd.n234 0.0496377
R514 vdd.n206 vdd.n186 0.038
R515 vdd.n195 vdd.n188 0.038
R516 vdd.n227 vdd.n226 0.038
R517 vdd.n238 vdd.n179 0.038
R518 vdd.n249 vdd.n248 0.0308751
R519 vdd.n175 vdd.n173 0.0308751
R520 vdd.n217 vdd.n212 0.0308751
R521 vdd.n216 vdd.n215 0.0308751
R522 vdd.n4 vdd.n2 0.0308751
R523 vdd.n169 vdd.n168 0.0308751
R524 vdd.n12 vdd.n11 0.0308751
R525 vdd.n13 vdd.n8 0.0308751
R526 vdd.n27 vdd.n25 0.0308751
R527 vdd.n32 vdd.n31 0.0308751
R528 vdd.n37 vdd.n35 0.0308751
R529 vdd.n42 vdd.n41 0.0308751
R530 vdd.n47 vdd.n45 0.0308751
R531 vdd.n52 vdd.n51 0.0308751
R532 vdd.n68 vdd.n66 0.0308751
R533 vdd.n140 vdd.n139 0.0308751
R534 vdd.n75 vdd.n74 0.0308751
R535 vdd.n76 vdd.n71 0.0308751
R536 vdd.n95 vdd.n93 0.0308751
R537 vdd.n104 vdd.n103 0.0308751
R538 vdd.n110 vdd.n109 0.0308751
R539 vdd.n111 vdd.n91 0.0308751
R540 vdd.n122 vdd.n121 0.0308751
R541 vdd.n123 vdd.n118 0.0308751
R542 vdd.n146 vdd.n145 0.0308751
R543 vdd.n147 vdd.n23 0.0308751
R544 vdd.n57 vdd.n55 0.0308751
R545 vdd.n62 vdd.n61 0.0308751
R546 vdd.n247 vdd.n174 0.0307722
R547 vdd.n246 vdd.n245 0.0307722
R548 vdd.n219 vdd.n218 0.0307722
R549 vdd.n213 vdd.n211 0.0307722
R550 vdd.n166 vdd.n165 0.0307722
R551 vdd.n167 vdd.n3 0.0307722
R552 vdd.n9 vdd.n7 0.0307722
R553 vdd.n15 vdd.n14 0.0307722
R554 vdd.n29 vdd.n28 0.0307722
R555 vdd.n30 vdd.n26 0.0307722
R556 vdd.n39 vdd.n38 0.0307722
R557 vdd.n40 vdd.n36 0.0307722
R558 vdd.n49 vdd.n48 0.0307722
R559 vdd.n50 vdd.n46 0.0307722
R560 vdd.n137 vdd.n136 0.0307722
R561 vdd.n138 vdd.n67 0.0307722
R562 vdd.n72 vdd.n70 0.0307722
R563 vdd.n78 vdd.n77 0.0307722
R564 vdd.n101 vdd.n100 0.0307722
R565 vdd.n102 vdd.n94 0.0307722
R566 vdd.n92 vdd.n90 0.0307722
R567 vdd.n113 vdd.n112 0.0307722
R568 vdd.n119 vdd.n117 0.0307722
R569 vdd.n125 vdd.n124 0.0307722
R570 vdd.n24 vdd.n22 0.0307722
R571 vdd.n149 vdd.n148 0.0307722
R572 vdd.n59 vdd.n58 0.0307722
R573 vdd.n60 vdd.n56 0.0307722
R574 vdd.n64 vdd.n54 0.0235488
R575 vdd.n54 vdd.n44 0.0235488
R576 vdd.n44 vdd.n34 0.0235488
R577 vdd.n34 vdd.n1 0.0235488
R578 vdd.n171 vdd.n1 0.0235488
R579 vdd.n143 vdd.n142 0.0235488
R580 vdd.n142 vdd.n65 0.0235488
R581 vdd.n106 vdd.n65 0.0235488
R582 vdd.n107 vdd.n106 0.0235488
R583 vdd.n107 vdd.n0 0.0235488
R584 vdd.n131 vdd.n130 0.00773882
R585 vdd vdd.n252 0.00527439
R586 vdd.n87 vdd.n6 0.00166667
R587 vdd.n129 vdd.n87 0.00133332
R588 vdd.n69 vdd.n6 0.001
R589 vdd.n132 vdd.n81 0.001
R590 vdd.n97 vdd.n84 0.001
R591 vdd.n89 vdd.n83 0.001
R592 vdd.n128 vdd.n82 0.001
R593 vdd.n129 vdd.n128 0.001
R594 vdd.n89 vdd.n82 0.001
R595 vdd.n97 vdd.n83 0.001
R596 vdd.n84 vdd.n81 0.001
R597 vdd.n132 vdd.n69 0.001
R598 gnd.n82 gnd.n81 2794.14
R599 gnd.n12 gnd.n11 17.0005
R600 gnd.n74 gnd.n64 17.0005
R601 gnd.n65 gnd.n64 17.0005
R602 gnd.n73 gnd.n64 17.0005
R603 gnd.n66 gnd.n64 17.0005
R604 gnd.n72 gnd.n64 17.0005
R605 gnd.n67 gnd.n64 17.0005
R606 gnd.n71 gnd.n64 17.0005
R607 gnd.n68 gnd.n64 17.0005
R608 gnd.n70 gnd.n64 17.0005
R609 gnd.n69 gnd.n64 17.0005
R610 gnd.n76 gnd.n64 17.0005
R611 gnd.n75 gnd.n74 17.0005
R612 gnd.n75 gnd.n65 17.0005
R613 gnd.n75 gnd.n73 17.0005
R614 gnd.n75 gnd.n66 17.0005
R615 gnd.n75 gnd.n72 17.0005
R616 gnd.n75 gnd.n67 17.0005
R617 gnd.n75 gnd.n71 17.0005
R618 gnd.n75 gnd.n68 17.0005
R619 gnd.n75 gnd.n70 17.0005
R620 gnd.n75 gnd.n69 17.0005
R621 gnd.n76 gnd.n75 17.0005
R622 gnd.n35 gnd.n34 17.0005
R623 gnd.n34 gnd.n33 17.0005
R624 gnd.n81 gnd.n53 17.0005
R625 gnd.n81 gnd.n54 17.0005
R626 gnd.n81 gnd.n55 17.0005
R627 gnd.n81 gnd.n56 17.0005
R628 gnd.n81 gnd.n57 17.0005
R629 gnd.n81 gnd.n58 17.0005
R630 gnd.n81 gnd.n59 17.0005
R631 gnd.n81 gnd.n60 17.0005
R632 gnd.n81 gnd.n61 17.0005
R633 gnd.n81 gnd.n62 17.0005
R634 gnd.n124 gnd.n108 17.0005
R635 gnd.n109 gnd.n108 17.0005
R636 gnd.n122 gnd.n108 17.0005
R637 gnd.n110 gnd.n108 17.0005
R638 gnd.n121 gnd.n108 17.0005
R639 gnd.n111 gnd.n108 17.0005
R640 gnd.n120 gnd.n108 17.0005
R641 gnd.n112 gnd.n108 17.0005
R642 gnd.n119 gnd.n108 17.0005
R643 gnd.n113 gnd.n108 17.0005
R644 gnd.n118 gnd.n108 17.0005
R645 gnd.n124 gnd.n123 17.0005
R646 gnd.n123 gnd.n109 17.0005
R647 gnd.n123 gnd.n122 17.0005
R648 gnd.n123 gnd.n110 17.0005
R649 gnd.n123 gnd.n121 17.0005
R650 gnd.n123 gnd.n111 17.0005
R651 gnd.n123 gnd.n120 17.0005
R652 gnd.n123 gnd.n112 17.0005
R653 gnd.n123 gnd.n119 17.0005
R654 gnd.n123 gnd.n113 17.0005
R655 gnd.n123 gnd.n118 17.0005
R656 gnd.n126 gnd.n85 17.0005
R657 gnd.n126 gnd.n86 17.0005
R658 gnd.n126 gnd.n87 17.0005
R659 gnd.n126 gnd.n88 17.0005
R660 gnd.n126 gnd.n89 17.0005
R661 gnd.n126 gnd.n90 17.0005
R662 gnd.n126 gnd.n91 17.0005
R663 gnd.n126 gnd.n92 17.0005
R664 gnd.n126 gnd.n93 17.0005
R665 gnd.n126 gnd.n94 17.0005
R666 gnd.n10 gnd.n9 15.0005
R667 gnd.n78 gnd.n77 15.0005
R668 gnd.n32 gnd.n31 15.0005
R669 gnd.n116 gnd.n115 15.0005
R670 gnd.n101 gnd.n19 8.501
R671 gnd.n101 gnd.n95 8.501
R672 gnd.n101 gnd.n100 8.501
R673 gnd.n101 gnd.n99 8.501
R674 gnd.n102 gnd.n101 8.501
R675 gnd.n28 gnd.n24 8.49127
R676 gnd.n28 gnd.n27 8.49127
R677 gnd.n29 gnd.n28 8.49127
R678 gnd.n34 gnd.n25 8.49127
R679 gnd.n34 gnd.n26 8.49127
R680 gnd.n15 gnd.n14 8.49123
R681 gnd.n14 gnd.n7 8.49123
R682 gnd.n14 gnd.n13 8.49123
R683 gnd.n11 gnd.n6 8.49123
R684 gnd.n11 gnd.n8 8.49123
R685 gnd.n104 gnd.n103 8.48464
R686 gnd.n107 gnd.n96 8.46519
R687 gnd.n106 gnd.n97 8.46519
R688 gnd.n105 gnd.n98 8.46519
R689 gnd.n126 gnd.n18 8.34456
R690 gnd.n101 gnd.n82 6.02053
R691 gnd.n45 gnd.n44 5.48318
R692 gnd.n129 gnd.n128 5.48318
R693 gnd.n41 gnd.n40 5.47768
R694 gnd.n51 gnd.n50 5.47768
R695 gnd.n14 gnd.n5 3.4169
R696 gnd.n28 gnd.n23 3.4022
R697 gnd.n34 gnd.n23 3.40192
R698 gnd.n126 gnd.n125 3.3033
R699 gnd.n126 gnd.n84 3.29867
R700 gnd.n127 gnd.n126 3.29859
R701 gnd.n81 gnd.n80 3.29855
R702 gnd.n81 gnd.n21 3.29832
R703 gnd.n126 gnd.n3 3.28305
R704 gnd.n81 gnd.n22 3.28288
R705 gnd.n11 gnd.n5 2.82281
R706 gnd.n126 gnd.n83 2.69969
R707 gnd.n81 gnd.n20 2.6991
R708 gnd.n126 gnd.n17 1.94103
R709 gnd.n81 gnd.n37 1.94046
R710 gnd.n126 gnd.n82 1.53748
R711 gnd.n52 gnd.n51 1.20601
R712 gnd.n50 gnd.n43 1.10932
R713 gnd.n45 gnd.n0 1.10932
R714 gnd.n42 gnd.n41 1.10932
R715 gnd.n130 gnd.n129 1.10932
R716 gnd.n2 gnd.n1 1.1005
R717 gnd.n39 gnd.n38 1.1005
R718 gnd.n47 gnd.n46 1.1005
R719 gnd.n49 gnd.n48 1.1005
R720 gnd.n81 gnd.n52 0.846373
R721 gnd.n74 gnd.n52 0.816125
R722 gnd.n40 gnd.n17 0.552785
R723 gnd.n51 gnd.n37 0.550694
R724 gnd.n17 gnd.n16 0.539211
R725 gnd.n37 gnd.n36 0.520006
R726 gnd.n125 gnd.n107 0.470337
R727 gnd.n30 gnd.n20 0.445273
R728 gnd.n83 gnd.n4 0.444434
R729 gnd.n36 gnd.n22 0.438499
R730 gnd.n114 gnd.n83 0.420793
R731 gnd.n63 gnd.n20 0.419889
R732 gnd.n16 gnd.n3 0.418292
R733 gnd.n44 gnd.n21 0.408383
R734 gnd.n128 gnd.n127 0.407974
R735 gnd.n40 gnd.n18 0.395917
R736 gnd.n43 gnd.n42 0.37285
R737 gnd.n104 gnd.n18 0.347109
R738 gnd.n80 gnd.n63 0.343886
R739 gnd.n114 gnd.n84 0.343268
R740 gnd.n127 gnd.n4 0.318914
R741 gnd.n30 gnd.n21 0.318498
R742 gnd.n44 gnd.n22 0.306266
R743 gnd.n128 gnd.n3 0.305337
R744 gnd.n117 gnd.n84 0.294788
R745 gnd.n80 gnd.n79 0.294146
R746 gnd.n106 gnd.n105 0.288586
R747 gnd.n107 gnd.n106 0.288586
R748 gnd.n105 gnd.n104 0.249692
R749 gnd.n33 gnd.n32 0.247403
R750 gnd.n125 gnd.n124 0.244402
R751 gnd.n12 gnd.n10 0.24324
R752 gnd.n10 gnd.n4 0.227375
R753 gnd.n79 gnd.n78 0.227375
R754 gnd.n78 gnd.n63 0.227375
R755 gnd.n32 gnd.n30 0.227375
R756 gnd.n117 gnd.n116 0.227375
R757 gnd.n116 gnd.n114 0.227375
R758 gnd.n131 gnd.n130 0.17199
R759 gnd.n36 gnd.n23 0.0828779
R760 gnd.n16 gnd.n5 0.0744717
R761 gnd.n7 gnd.n6 0.0405896
R762 gnd.n13 gnd.n8 0.0405896
R763 gnd.n15 gnd.n6 0.0405896
R764 gnd.n8 gnd.n7 0.0405896
R765 gnd.n27 gnd.n25 0.0404028
R766 gnd.n29 gnd.n26 0.0404028
R767 gnd.n25 gnd.n24 0.0404028
R768 gnd.n27 gnd.n26 0.0404028
R769 gnd.n74 gnd.n53 0.0275956
R770 gnd.n124 gnd.n94 0.0275956
R771 gnd.n65 gnd.n54 0.0267868
R772 gnd.n109 gnd.n93 0.0267868
R773 gnd.n73 gnd.n55 0.0259779
R774 gnd.n122 gnd.n92 0.0259779
R775 gnd.n66 gnd.n56 0.0247647
R776 gnd.n110 gnd.n91 0.0247647
R777 gnd.n131 gnd.n0 0.02459
R778 gnd.n72 gnd.n57 0.0239559
R779 gnd.n121 gnd.n90 0.0239559
R780 gnd.n67 gnd.n58 0.0231471
R781 gnd.n111 gnd.n89 0.0231471
R782 gnd.n49 gnd.n46 0.023
R783 gnd.n39 gnd.n2 0.023
R784 gnd.n71 gnd.n59 0.0223382
R785 gnd.n120 gnd.n88 0.0223382
R786 gnd.n68 gnd.n60 0.021125
R787 gnd.n112 gnd.n87 0.021125
R788 gnd.n16 gnd.n15 0.0205448
R789 gnd.n13 gnd.n12 0.0205448
R790 gnd.n35 gnd.n24 0.0204514
R791 gnd.n33 gnd.n29 0.0204514
R792 gnd.n70 gnd.n61 0.0203162
R793 gnd.n119 gnd.n86 0.0203162
R794 gnd.n69 gnd.n62 0.0195074
R795 gnd.n113 gnd.n85 0.0195074
R796 gnd.n38 gnd.n1 0.01425
R797 gnd.n48 gnd.n47 0.01425
R798 gnd.n79 gnd.n76 0.0126324
R799 gnd.n118 gnd.n117 0.0126324
R800 gnd.n76 gnd.n62 0.0114191
R801 gnd.n118 gnd.n85 0.0114191
R802 gnd.n42 gnd.n38 0.01128
R803 gnd.n130 gnd.n1 0.01128
R804 gnd.n48 gnd.n43 0.01128
R805 gnd.n47 gnd.n0 0.01128
R806 gnd.n69 gnd.n61 0.0106103
R807 gnd.n113 gnd.n86 0.0106103
R808 gnd.n70 gnd.n60 0.00980147
R809 gnd.n119 gnd.n87 0.00980147
R810 gnd.n50 gnd.n49 0.00932
R811 gnd.n46 gnd.n45 0.00932
R812 gnd.n41 gnd.n39 0.00932
R813 gnd.n129 gnd.n2 0.00932
R814 gnd.n68 gnd.n59 0.00858823
R815 gnd.n112 gnd.n88 0.00858823
R816 gnd.n71 gnd.n58 0.00777941
R817 gnd.n120 gnd.n89 0.00777941
R818 gnd.n67 gnd.n57 0.00697059
R819 gnd.n111 gnd.n90 0.00697059
R820 gnd.n72 gnd.n56 0.00616176
R821 gnd.n121 gnd.n91 0.00616176
R822 gnd.n36 gnd.n35 0.00576316
R823 gnd.n66 gnd.n55 0.00494853
R824 gnd.n110 gnd.n92 0.00494853
R825 gnd.n73 gnd.n54 0.00413971
R826 gnd.n122 gnd.n93 0.00413971
R827 gnd.n65 gnd.n53 0.00333088
R828 gnd.n109 gnd.n94 0.00333088
R829 gnd.n131 gnd 0.0014625
R830 gnd.n126 gnd.n19 0.001
R831 gnd.n103 gnd.n102 0.001
R832 gnd.n99 gnd.n98 0.001
R833 gnd.n100 gnd.n97 0.001
R834 gnd.n96 gnd.n95 0.001
R835 gnd.n103 gnd.n19 0.001
R836 gnd.n126 gnd.n95 0.001
R837 gnd.n100 gnd.n96 0.001
R838 gnd.n99 gnd.n97 0.001
R839 gnd.n102 gnd.n98 0.001
C37 vbias gnd 2.83431f
C38 clk gnd 7.89606f
C39 out+ gnd 2.36194f
C40 out- gnd 2.35875f
C41 V+ gnd 3.9126f
C42 V- gnd 3.93119f
C43 vdd gnd 17.9739f
C44 a_1752_817# gnd 0.44266f $ **FLOATING
C45 a_944_1911# gnd 4.28617f $ **FLOATING
C46 a_687_2445# gnd 4.01269f $ **FLOATING
C47 a_1245_3300# gnd 1.43203f $ **FLOATING
.ends
\\"
"
}
V {}
S {}
E {}
L 4 -130 -100 130 0 {}
L 4 -130 100 130 0 {}
L 4 -130 -100 -130 100 {}
L 4 -150 0 -130 0 {}
L 4 -150 -60 -130 -60 {}
L 4 -150 60 -130 60 {}
L 4 110 10 130 10 {}
L 4 110 -10 130 -10 {}
L 4 -20 60 -20 80 {}
L 7 -70 -100 -70 -80 {}
L 7 -70 80 -70 100 {}
B 5 -72.5 -102.5 -67.5 -97.5 {name=vdd dir=inout}
B 5 -152.5 -2.5 -147.5 2.5 {name=vbias dir=in}
B 5 -152.5 -62.5 -147.5 -57.5 {name=v+ dir=in}
B 5 -152.5 57.5 -147.5 62.5 {name=v- dir=in}
B 5 127.5 7.5 132.5 12.5 {name=out- dir=out}
B 5 127.5 -12.5 132.5 -7.5 {name=out+ dir=out}
B 5 -22.5 77.5 -17.5 82.5 {name=clk dir=in}
B 5 -72.5 97.5 -67.5 102.5 {name=gnd dir=inout}
T {@symname} -89 -6 0 0 0.3 0.3 {}
T {@name} 25 -52 0 0 0.2 0.2 {}
T {vdd} -74 -75 3 1 0.2 0.2 {}
T {vbias} -125 -4 0 0 0.2 0.2 {}
T {v+} -125 -64 0 0 0.2 0.2 {}
T {v-} -125 56 0 0 0.2 0.2 {}
T {out-} 90 1 0 1 0.2 0.2 {}
T {out+} 95 -14 0 1 0.2 0.2 {}
T {clk} -24 55 3 0 0.2 0.2 {}
T {gnd} -66 75 1 1 0.2 0.2 {}

227
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/schematic/dynamic_comparator.sch → modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/xschem_post_layout/schematic/DIFF_COMPARATOR.sch
View File

@ -8,93 +8,69 @@ N 490 -650 490 -600 {
lab=#net1}
N 810 -650 810 -600 {
lab=#net1}
N 550 -830 610 -830 {
lab=vbias}
N 650 -930 1060 -930 {
lab=vdd}
N 650 -800 650 -770 {
lab=#net2}
N 1060 -470 1060 -450 {
lab=out-}
N 980 -530 1020 -530 {
lab=#net3}
lab=#net2}
N 980 -470 980 -420 {
lab=#net3}
lab=#net2}
N 980 -420 1020 -420 {
lab=#net3}
N 1060 -930 1060 -530 {
lab=vdd}
lab=#net2}
N 810 -540 810 -470 {
lab=#net3}
lab=#net2}
N 810 -470 980 -470 {
lab=#net3}
lab=#net2}
N 980 -530 980 -470 {
lab=#net3}
lab=#net2}
N 720 -270 720 -230 {
lab=#net3}
lab=#net2}
N 810 -270 900 -270 {
lab=#net3}
lab=#net2}
N 900 -270 900 -230 {
lab=#net3}
lab=#net2}
N 810 -470 810 -270 {
lab=#net3}
lab=#net2}
N 720 -270 810 -270 {
lab=#net3}
N 810 -130 900 -130 {
lab=gnd}
lab=#net2}
N 900 -170 900 -130 {
lab=gnd}
N 720 -170 720 -130 {
lab=gnd}
N 810 -200 900 -200 {
lab=gnd}
N 400 -270 400 -230 {
lab=#net4}
lab=#net3}
N 490 -270 580 -270 {
lab=#net4}
lab=#net3}
N 580 -270 580 -230 {
lab=#net4}
lab=#net3}
N 400 -270 490 -270 {
lab=#net4}
N 490 -130 580 -130 {
lab=gnd}
lab=#net3}
N 580 -170 580 -130 {
lab=gnd}
N 400 -170 400 -130 {
lab=gnd}
N 490 -200 580 -200 {
lab=gnd}
N 650 -650 810 -650 {
lab=#net1}
N 650 -710 650 -650 {
lab=#net1}
N 490 -650 650 -650 {
lab=#net1}
N 650 -930 650 -830 {
lab=vdd}
N 650 -740 700 -740 {
lab=vdd}
N 490 -570 810 -570 {
lab=vdd}
N 320 -470 490 -470 {
lab=#net4}
lab=#net3}
N 490 -470 490 -270 {
lab=#net4}
lab=#net3}
N 490 -540 490 -470 {
lab=#net4}
lab=#net3}
N 240 -470 240 -450 {
lab=out+}
N 280 -530 320 -530 {
lab=#net4}
lab=#net3}
N 320 -470 320 -420 {
lab=#net4}
lab=#net3}
N 280 -420 320 -420 {
lab=#net4}
lab=#net3}
N 320 -530 320 -470 {
lab=#net4}
N 240 -930 240 -530 {
lab=vdd}
N 240 -930 650 -930 {
lab=#net3}
N 650 -930 1060 -930 {
lab=vdd}
N 240 -130 400 -130 {
lab=gnd}
@ -103,9 +79,9 @@ lab=gnd}
N 900 -130 1060 -130 {
lab=gnd}
N 490 -470 680 -200 {
lab=#net4}
N 620 -200 810 -470 {
lab=#net3}
N 620 -200 810 -470 {
lab=#net2}
N 140 -470 240 -470 {
lab=out+}
N 240 -500 240 -470 {
@ -114,80 +90,81 @@ N 1060 -470 1160 -470 {
lab=out-}
N 1060 -500 1060 -470 {
lab=out-}
N 330 -200 360 -200 {
N 340 -200 360 -200 {
lab=clk}
N 440 -570 450 -570 {
lab=v+}
N 850 -570 860 -570 {
lab=v-}
N 360 -740 610 -740 {
lab=clk}
N 360 -740 360 -200 {
lab=clk}
N 1060 -420 1060 -130 {
N 720 -130 900 -130 {
lab=gnd}
N 810 -200 810 -130 {
lab=gnd}
N 720 -200 810 -200 {
lab=gnd}
N 720 -130 810 -130 {
lab=gnd}
N 490 -200 490 -130 {
lab=gnd}
N 400 -200 490 -200 {
lab=gnd}
N 400 -130 490 -130 {
lab=gnd}
N 240 -420 240 -130 {
N 400 -130 580 -130 {
lab=gnd}
N 940 -200 960 -200 {
lab=clk}
N 1500 -340 1500 -320 {lab=well}
N 1500 -260 1500 -240 {lab=vdd}
N 490 -570 810 -570 {
lab=well}
N 1240 -360 1240 -330 {lab=gnd}
N 1240 -360 1280 -360 {lab=gnd}
N 1280 -360 1280 -240 {lab=gnd}
N 1240 -240 1280 -240 {lab=gnd}
N 1240 -270 1240 -240 {lab=gnd}
N 1190 -300 1240 -300 {lab=sub}
N 1370 -270 1370 -250 {lab=gnd}
N 400 -200 580 -200 {
lab=sub}
N 720 -200 900 -200 {
lab=sub}
N 240 -390 240 -130 {lab=gnd}
N 1370 -340 1370 -330 {lab=sub}
N 1060 -420 1110 -420 {lab=sub}
N 190 -420 240 -420 {lab=sub}
N 1060 -390 1060 -130 {lab=gnd}
N 1060 -930 1060 -560 {lab=vdd}
N 240 -930 240 -560 {lab=vdd}
N 1060 -530 1110 -530 {lab=well}
N 190 -530 240 -530 {lab=well}
N 650 -810 650 -770 {lab=#net4}
N 650 -930 650 -870 {lab=vdd}
N 240 -930 650 -930 {
lab=vdd}
N 340 -740 340 -200 {lab=clk}
N 330 -200 340 -200 {
lab=clk}
N 340 -740 610 -740 {lab=clk}
N 580 -840 610 -840 {lab=vbias}
N 650 -740 710 -740 {lab=well}
N 650 -840 710 -840 {lab=well}
N 710 -840 710 -740 {lab=well}
C {iopin.sym} 1060 -930 0 0 {name=p1 lab=vdd}
C {iopin.sym} 1060 -130 0 0 {name=p2 lab=gnd}
C {ipin.sym} 440 -570 0 0 {name=p3 lab=v+}
C {ipin.sym} 860 -570 0 1 {name=p4 lab=v-}
C {ipin.sym} 550 -830 0 0 {name=p5 lab=vbias}
C {ipin.sym} 330 -200 0 0 {name=p6 lab=clk}
C {opin.sym} 1160 -470 0 0 {name=p7 lab=out-}
C {opin.sym} 140 -470 0 1 {name=p8 lab=out+}
C {lab_pin.sym} 650 -570 3 0 {name=p9 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 700 -740 2 0 {name=p10 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 630 -740 0 0 {name=M13
l=0.3u
w=18u
ng=3
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 630 -830 0 0 {name=M3
l=0.3u
w=18u
ng=3
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 470 -570 0 0 {name=M2
l=200n
w=32u
ng=4
m=1
w=8u
ng=2
m=4
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 830 -570 0 1 {name=M1
l=200n
w=32u
ng=4
m=1
w=8u
ng=2
m=4
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 1040 -530 0 0 {name=M4
l=0.200u
w=8u
ng=1
ng=2
m=1
model=sg13_lv_pmos
spiceprefix=X
@ -195,7 +172,7 @@ spiceprefix=X
C {sg13g2_pr/sg13_lv_pmos.sym} 260 -530 0 1 {name=M5
l=0.200u
w=8u
ng=1
ng=2
m=1
model=sg13_lv_pmos
spiceprefix=X
@ -203,7 +180,7 @@ spiceprefix=X
C {sg13g2_pr/sg13_lv_nmos.sym} 260 -420 2 0 {name=M11
l=0.200u
w=4.0u
ng=1
ng=2
m=1
model=sg13_lv_nmos
spiceprefix=X
@ -211,7 +188,7 @@ spiceprefix=X
C {sg13g2_pr/sg13_lv_nmos.sym} 1040 -420 2 1 {name=M12
l=0.200u
w=4.0u
ng=1
ng=2
m=1
model=sg13_lv_nmos
spiceprefix=X
@ -249,3 +226,59 @@ model=sg13_lv_nmos
spiceprefix=X
}
C {lab_pin.sym} 960 -200 2 0 {name=p11 sig_type=std_logic lab=clk}
C {sg13g2_pr/ntap1.sym} 1500 -290 2 0 {name=R1
model=ntap1
spiceprefix=X
w=100e-6
l=100e-6
}
C {lab_pin.sym} 1500 -240 2 0 {name=p9 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_nmos.sym} 1260 -300 0 1 {name=M3
l=0.200u
w=4.0u
ng=1
m=4
model=sg13_lv_nmos
spiceprefix=X
}
C {lab_pin.sym} 1190 -300 0 0 {name=p10 sig_type=std_logic lab=sub
m=4}
C {lab_pin.sym} 1240 -360 0 0 {name=p12 sig_type=std_logic lab=gnd
m=4}
C {sg13g2_pr/ptap1.sym} 1370 -300 2 0 {name=R2
model=ptap1
spiceprefix=X
w=100e-6
l=100e-6
}
C {lab_pin.sym} 1370 -250 0 0 {name=p13 sig_type=std_logic lab=gnd
m=4}
C {lab_pin.sym} 820 -200 3 0 {name=p14 sig_type=std_logic lab=sub}
C {lab_pin.sym} 490 -200 3 0 {name=p15 sig_type=std_logic lab=sub}
C {lab_pin.sym} 1370 -340 0 1 {name=p16 sig_type=std_logic lab=sub}
C {lab_pin.sym} 1500 -340 0 1 {name=p17 sig_type=std_logic lab=well}
C {lab_pin.sym} 660 -570 1 1 {name=p18 sig_type=std_logic lab=well}
C {lab_pin.sym} 1110 -530 0 1 {name=p19 sig_type=std_logic lab=well}
C {lab_pin.sym} 190 -530 2 1 {name=p20 sig_type=std_logic lab=well}
C {lab_pin.sym} 1110 -420 0 1 {name=p21 sig_type=std_logic lab=sub}
C {lab_pin.sym} 190 -420 2 1 {name=p22 sig_type=std_logic lab=sub}
C {sg13g2_pr/sg13_lv_pmos.sym} 630 -740 0 0 {name=M13
l=0.3u
w=18u
ng=4
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 630 -840 0 0 {name=M9
l=0.3u
w=18u
ng=4
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {ipin.sym} 580 -840 0 0 {name=p5 lab=vbias}
C {lab_pin.sym} 710 -790 0 1 {name=p23 sig_type=std_logic lab=well}
C {sg13g2_pr/annotate_fet_params.sym} 240 -400 0 0 {name=annot1 ref=M1}

39
modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/xschem_post_layout/schematic/DIFF_COMPARATOR.sym Normal file
View File

@ -0,0 +1,39 @@
v {xschem version=3.4.5 file_version=1.2
}
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -130 -100 130 0 {}
L 4 -130 100 130 0 {}
L 4 -130 -100 -130 100 {}
L 4 -150 0 -130 0 {}
L 4 -150 -60 -130 -60 {}
L 4 -150 60 -130 60 {}
L 4 110 10 130 10 {}
L 4 110 -10 130 -10 {}
L 4 -20 60 -20 80 {}
L 7 -70 -100 -70 -80 {}
L 7 -70 80 -70 100 {}
B 5 -72.5 -102.5 -67.5 -97.5 {name=vdd dir=inout}
B 5 -152.5 -2.5 -147.5 2.5 {name=vbias dir=in}
B 5 -152.5 -62.5 -147.5 -57.5 {name=v+ dir=in}
B 5 -152.5 57.5 -147.5 62.5 {name=v- dir=in}
B 5 127.5 7.5 132.5 12.5 {name=out- dir=out}
B 5 127.5 -12.5 132.5 -7.5 {name=out+ dir=out}
B 5 -22.5 77.5 -17.5 82.5 {name=clk dir=in}
B 5 -72.5 97.5 -67.5 102.5 {name=gnd dir=inout}
T {@symname} -89 -6 0 0 0.3 0.3 {}
T {@name} 25 -52 0 0 0.2 0.2 {}
T {vdd} -74 -75 3 1 0.2 0.2 {}
T {vbias} -125 -4 0 0 0.2 0.2 {}
T {v+} -125 -64 0 0 0.2 0.2 {}
T {v-} -125 56 0 0 0.2 0.2 {}
T {out-} 90 1 0 1 0.2 0.2 {}
T {out+} 95 -14 0 1 0.2 0.2 {}
T {clk} -24 55 3 0 0.2 0.2 {}
T {gnd} -66 75 1 1 0.2 0.2 {}

285
modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/xschem_post_layout/testbench/comparator_tb.sch Normal file
View File

@ -0,0 +1,285 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
B 2 20 -1225 820 -825 {flags=graph
y1=0
y2=1.3
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
divx=5
subdivx=4
xlabmag=1.0
ylabmag=1.0
dataset=-1
unitx=1
logx=0
logy=0
x2=1e-06
color=4
node=clk}
B 2 20 -855 820 -455 {flags=graph
y1=0.59
y2=0.61
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
divx=5
subdivx=4
xlabmag=1.0
ylabmag=1.0
dataset=-1
unitx=1
logx=0
logy=0
x2=1e-06
color=4
node=vinp}
B 2 850 -1225 1650 -825 {flags=graph
y1=-1.3
y2=1.3
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
divx=5
subdivx=4
xlabmag=1.0
ylabmag=1.0
dataset=-1
unitx=1
logx=0
logy=0
x2=1e-06
color=4
node=vout}
B 2 850 -805 1650 -405 {flags=graph
y1=1.1
y2=1.2
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
divx=5
subdivx=4
xlabmag=1.0
ylabmag=1.0
dataset=-1
unitx=1
logx=0
logy=0
x2=1e-06
color=4
node=outp}
B 2 850 -395 1650 5 {flags=graph
y1=0.24502661
y2=1.4615386
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
divx=5
subdivx=4
xlabmag=1.0
ylabmag=1.0
dataset=-1
unitx=1
logx=0
logy=0
x2=1e-06
color=4
node=outm}
N -540 -180 -540 -160 {
lab=vbias}
N -610 -180 -610 -160 {
lab=vdd}
N -610 -100 -610 -80 {
lab=GND}
N -570 -80 -540 -80 {
lab=GND}
N -420 -180 -420 -160 {
lab=clk}
N -420 -100 -420 -70 {
lab=GND}
N -570 -80 -570 -70 {
lab=GND}
N -420 -70 -210 -70 {
lab=GND}
N -210 -100 -210 -70 {
lab=GND}
N -210 -180 -210 -160 {
lab=vinp}
N 60 -220 120 -220 {
lab=vbias}
N 200 -120 200 -90 {
lab=GND}
N 250 -140 250 -110 {
lab=clk}
N 200 -350 200 -320 {
lab=vdd}
N 80 -160 120 -160 {
lab=vbias}
N 80 -280 120 -280 {
lab=vinp}
N -610 -80 -570 -80 {
lab=GND}
N -540 -100 -540 -80 {
lab=GND}
N 60 -280 80 -280 {
lab=vinp}
N 80 -160 80 -140 {
lab=vbias}
N 60 -160 80 -160 {
lab=vbias}
N 80 -80 80 -60 {
lab=GND}
N 460 -150 460 -140 {
lab=GND}
N 460 -300 460 -290 {
lab=GND}
N 80 -300 80 -280 {
lab=vinp}
N 80 -380 80 -360 {
lab=GND}
N 390 -230 500 -230 {lab=outp}
N 390 -210 500 -210 {lab=outm}
C {devices/code_shown.sym} -855 -630 0 0 {name=MODEL only_toplevel=false
format="tcleval( @value )"
value="
.lib cornerMOSlv.lib mos_tt
.lib cornerRES.lib res_typ
"}
C {devices/code_shown.sym} -865 -1040 0 0 {name=NGSPICE only_toplevel=false
value="
.param temp=27
.param clock = 100e6 ; 100 MHz clock
.param period = \{1/clock\}
.param num_cycles = 100
.param tr = \{num_cycles * period\}
.control
save all
* Operating point simulation
op
write comparator_tb.raw
set appendwrite
* Transient analysis
tran 500p 1u
let vindiff = v(vinp) - v(vbias)
let clk = v(clk)
let vout = v(outp) - v(outm)
write comparator_tb.raw
.endc
"}
C {vsource.sym} -610 -130 0 0 {name=V3 value="DC 1.2"}
C {vsource.sym} -540 -130 0 0 {name=V4 value="DC 0.6"}
C {gnd.sym} -310 -70 0 0 {name=l1 lab=GND}
C {lab_pin.sym} -540 -180 2 0 {name=p3 sig_type=std_logic lab=vbias}
C {lab_pin.sym} -610 -180 2 0 {name=p4 sig_type=std_logic lab=vdd}
C {vsource.sym} -420 -130 0 0 {name=V1 value="PULSE(0 1.2 0 0 0 5N \{period\})"}
C {lab_pin.sym} -420 -180 2 0 {name=p1 sig_type=std_logic lab=clk}
C {gnd.sym} -570 -70 0 0 {name=l2 lab=GND}
C {vsource.sym} -210 -130 0 0 {name=V2 value="PULSE(595e-3 605e-3 0 tr 1S 1S)"}
C {lab_pin.sym} -210 -180 2 0 {name=p2 sig_type=std_logic lab=vinp}
C {lab_pin.sym} 60 -280 2 1 {name=p5 sig_type=std_logic lab=vinp}
C {lab_pin.sym} 200 -350 2 0 {name=p6 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 60 -220 2 1 {name=p7 sig_type=std_logic lab=vbias}
C {lab_pin.sym} 60 -160 2 1 {name=p8 sig_type=std_logic lab=vbias}
C {lab_pin.sym} 250 -110 2 0 {name=p9 sig_type=std_logic lab=clk}
C {gnd.sym} 200 -90 0 0 {name=l3 lab=GND}
C {lab_pin.sym} 500 -230 2 0 {name=p10 sig_type=std_logic lab=outp}
C {lab_pin.sym} 500 -210 2 0 {name=p11 sig_type=std_logic lab=outm}
C {capa.sym} 80 -110 0 0 {name=C1
m=1
value=6.4p
footprint=1206
device="ceramic capacitor"}
C {gnd.sym} 80 -60 0 0 {name=l4 lab=GND}
C {gnd.sym} 80 -380 2 0 {name=l5 lab=GND}
C {capa.sym} 80 -330 2 0 {name=C2
m=1
value=6.4p
footprint=1206
device="ceramic capacitor"}
C {capa.sym} 460 -260 2 0 {name=C4
m=1
value=50f
footprint=1206
device="ceramic capacitor"}
C {capa.sym} 460 -180 0 0 {name=C3
m=1
value=50f
footprint=1206
device="ceramic capacitor"}
C {gnd.sym} 460 -140 0 0 {name=l6 lab=GND}
C {gnd.sym} 460 -300 2 0 {name=l7 lab=GND}
C {devices/launcher.sym} -210 -810 0 0 {name=h1
descr="OP annotate"
tclcommand="xschem annotate_op"
}
C {launcher.sym} -210 -850 0 0 {name=h5
descr="load waves"
tclcommand="xschem raw_read $netlist_dir/comparator_tb.raw tran"
}
C {launcher.sym} -210 -755 0 0 {name=h2
descr=SimulateNGSPICE
tclcommand="
# Setup the default simulation commands if not already set up
# for example by already launched simulations.
set_sim_defaults
puts $sim(spice,1,cmd)
# Change the Xyce command. In the spice category there are currently
# 5 commands (0, 1, 2, 3, 4). Command 3 is the Xyce batch
# you can get the number by querying $sim(spice,n)
set sim(spice,1,cmd) \{ngspice \\"$N\\" -a\}
# change the simulator to be used (Xyce)
set sim(spice,default) 0
# Create FET and BIP .save file
mkdir -p $netlist_dir
write_data [save_params] $netlist_dir/[file rootname [file tail [xschem get current_name]]].save
# run netlist and simulation
xschem netlist
simulate
"}
C {DIFF_COMPARATOR.sym} 270 -220 0 0 {name=x1}

1047
modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/xschem_post_layout/testbench/offset_MC_analysis.sch Normal file
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132
modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/xschem_post_layout/testbench/simulations/comparator_tb.save Normal file
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@ -0,0 +1,132 @@
* Place this .save file with a .include line in your testbench
.save @n.x1.xm2.nsg13_lv_pmos[ids]
.save @n.x1.xm2.nsg13_lv_pmos[gm]
.save @n.x1.xm2.nsg13_lv_pmos[gds]
.save @n.x1.xm2.nsg13_lv_pmos[vth]
.save @n.x1.xm2.nsg13_lv_pmos[vgs]
.save @n.x1.xm2.nsg13_lv_pmos[vdss]
.save @n.x1.xm2.nsg13_lv_pmos[vds]
.save @n.x1.xm2.nsg13_lv_pmos[cgg]
.save @n.x1.xm2.nsg13_lv_pmos[cgsol]
.save @n.x1.xm2.nsg13_lv_pmos[cgdol]
.save @n.x1.xm1.nsg13_lv_pmos[ids]
.save @n.x1.xm1.nsg13_lv_pmos[gm]
.save @n.x1.xm1.nsg13_lv_pmos[gds]
.save @n.x1.xm1.nsg13_lv_pmos[vth]
.save @n.x1.xm1.nsg13_lv_pmos[vgs]
.save @n.x1.xm1.nsg13_lv_pmos[vdss]
.save @n.x1.xm1.nsg13_lv_pmos[vds]
.save @n.x1.xm1.nsg13_lv_pmos[cgg]
.save @n.x1.xm1.nsg13_lv_pmos[cgsol]
.save @n.x1.xm1.nsg13_lv_pmos[cgdol]
.save @n.x1.xm4.nsg13_lv_pmos[ids]
.save @n.x1.xm4.nsg13_lv_pmos[gm]
.save @n.x1.xm4.nsg13_lv_pmos[gds]
.save @n.x1.xm4.nsg13_lv_pmos[vth]
.save @n.x1.xm4.nsg13_lv_pmos[vgs]
.save @n.x1.xm4.nsg13_lv_pmos[vdss]
.save @n.x1.xm4.nsg13_lv_pmos[vds]
.save @n.x1.xm4.nsg13_lv_pmos[cgg]
.save @n.x1.xm4.nsg13_lv_pmos[cgsol]
.save @n.x1.xm4.nsg13_lv_pmos[cgdol]
.save @n.x1.xm5.nsg13_lv_pmos[ids]
.save @n.x1.xm5.nsg13_lv_pmos[gm]
.save @n.x1.xm5.nsg13_lv_pmos[gds]
.save @n.x1.xm5.nsg13_lv_pmos[vth]
.save @n.x1.xm5.nsg13_lv_pmos[vgs]
.save @n.x1.xm5.nsg13_lv_pmos[vdss]
.save @n.x1.xm5.nsg13_lv_pmos[vds]
.save @n.x1.xm5.nsg13_lv_pmos[cgg]
.save @n.x1.xm5.nsg13_lv_pmos[cgsol]
.save @n.x1.xm5.nsg13_lv_pmos[cgdol]
.save @n.x1.xm11.nsg13_lv_nmos[ids]
.save @n.x1.xm11.nsg13_lv_nmos[gm]
.save @n.x1.xm11.nsg13_lv_nmos[gds]
.save @n.x1.xm11.nsg13_lv_nmos[vth]
.save @n.x1.xm11.nsg13_lv_nmos[vgs]
.save @n.x1.xm11.nsg13_lv_nmos[vdss]
.save @n.x1.xm11.nsg13_lv_nmos[vds]
.save @n.x1.xm11.nsg13_lv_nmos[cgg]
.save @n.x1.xm11.nsg13_lv_nmos[cgsol]
.save @n.x1.xm11.nsg13_lv_nmos[cgdol]
.save @n.x1.xm12.nsg13_lv_nmos[ids]
.save @n.x1.xm12.nsg13_lv_nmos[gm]
.save @n.x1.xm12.nsg13_lv_nmos[gds]
.save @n.x1.xm12.nsg13_lv_nmos[vth]
.save @n.x1.xm12.nsg13_lv_nmos[vgs]
.save @n.x1.xm12.nsg13_lv_nmos[vdss]
.save @n.x1.xm12.nsg13_lv_nmos[vds]
.save @n.x1.xm12.nsg13_lv_nmos[cgg]
.save @n.x1.xm12.nsg13_lv_nmos[cgsol]
.save @n.x1.xm12.nsg13_lv_nmos[cgdol]
.save @n.x1.xm6.nsg13_lv_nmos[ids]
.save @n.x1.xm6.nsg13_lv_nmos[gm]
.save @n.x1.xm6.nsg13_lv_nmos[gds]
.save @n.x1.xm6.nsg13_lv_nmos[vth]
.save @n.x1.xm6.nsg13_lv_nmos[vgs]
.save @n.x1.xm6.nsg13_lv_nmos[vdss]
.save @n.x1.xm6.nsg13_lv_nmos[vds]
.save @n.x1.xm6.nsg13_lv_nmos[cgg]
.save @n.x1.xm6.nsg13_lv_nmos[cgsol]
.save @n.x1.xm6.nsg13_lv_nmos[cgdol]
.save @n.x1.xm10.nsg13_lv_nmos[ids]
.save @n.x1.xm10.nsg13_lv_nmos[gm]
.save @n.x1.xm10.nsg13_lv_nmos[gds]
.save @n.x1.xm10.nsg13_lv_nmos[vth]
.save @n.x1.xm10.nsg13_lv_nmos[vgs]
.save @n.x1.xm10.nsg13_lv_nmos[vdss]
.save @n.x1.xm10.nsg13_lv_nmos[vds]
.save @n.x1.xm10.nsg13_lv_nmos[cgg]
.save @n.x1.xm10.nsg13_lv_nmos[cgsol]
.save @n.x1.xm10.nsg13_lv_nmos[cgdol]
.save @n.x1.xm7.nsg13_lv_nmos[ids]
.save @n.x1.xm7.nsg13_lv_nmos[gm]
.save @n.x1.xm7.nsg13_lv_nmos[gds]
.save @n.x1.xm7.nsg13_lv_nmos[vth]
.save @n.x1.xm7.nsg13_lv_nmos[vgs]
.save @n.x1.xm7.nsg13_lv_nmos[vdss]
.save @n.x1.xm7.nsg13_lv_nmos[vds]
.save @n.x1.xm7.nsg13_lv_nmos[cgg]
.save @n.x1.xm7.nsg13_lv_nmos[cgsol]
.save @n.x1.xm7.nsg13_lv_nmos[cgdol]
.save @n.x1.xm8.nsg13_lv_nmos[ids]
.save @n.x1.xm8.nsg13_lv_nmos[gm]
.save @n.x1.xm8.nsg13_lv_nmos[gds]
.save @n.x1.xm8.nsg13_lv_nmos[vth]
.save @n.x1.xm8.nsg13_lv_nmos[vgs]
.save @n.x1.xm8.nsg13_lv_nmos[vdss]
.save @n.x1.xm8.nsg13_lv_nmos[vds]
.save @n.x1.xm8.nsg13_lv_nmos[cgg]
.save @n.x1.xm8.nsg13_lv_nmos[cgsol]
.save @n.x1.xm8.nsg13_lv_nmos[cgdol]
.save @n.x1.xm3.nsg13_lv_nmos[ids]
.save @n.x1.xm3.nsg13_lv_nmos[gm]
.save @n.x1.xm3.nsg13_lv_nmos[gds]
.save @n.x1.xm3.nsg13_lv_nmos[vth]
.save @n.x1.xm3.nsg13_lv_nmos[vgs]
.save @n.x1.xm3.nsg13_lv_nmos[vdss]
.save @n.x1.xm3.nsg13_lv_nmos[vds]
.save @n.x1.xm3.nsg13_lv_nmos[cgg]
.save @n.x1.xm3.nsg13_lv_nmos[cgsol]
.save @n.x1.xm3.nsg13_lv_nmos[cgdol]
.save @n.x1.xm13.nsg13_lv_pmos[ids]
.save @n.x1.xm13.nsg13_lv_pmos[gm]
.save @n.x1.xm13.nsg13_lv_pmos[gds]
.save @n.x1.xm13.nsg13_lv_pmos[vth]
.save @n.x1.xm13.nsg13_lv_pmos[vgs]
.save @n.x1.xm13.nsg13_lv_pmos[vdss]
.save @n.x1.xm13.nsg13_lv_pmos[vds]
.save @n.x1.xm13.nsg13_lv_pmos[cgg]
.save @n.x1.xm13.nsg13_lv_pmos[cgsol]
.save @n.x1.xm13.nsg13_lv_pmos[cgdol]
.save @n.x1.xm9.nsg13_lv_pmos[ids]
.save @n.x1.xm9.nsg13_lv_pmos[gm]
.save @n.x1.xm9.nsg13_lv_pmos[gds]
.save @n.x1.xm9.nsg13_lv_pmos[vth]
.save @n.x1.xm9.nsg13_lv_pmos[vgs]
.save @n.x1.xm9.nsg13_lv_pmos[vdss]
.save @n.x1.xm9.nsg13_lv_pmos[vds]
.save @n.x1.xm9.nsg13_lv_pmos[cgg]
.save @n.x1.xm9.nsg13_lv_pmos[cgsol]
.save @n.x1.xm9.nsg13_lv_pmos[cgdol]

120
modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/xschem_post_layout/testbench/statistical_calculation/calculate_histogram.py Normal file
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@ -0,0 +1,120 @@
import numpy as np
import sys
import os
import matplotlib.pyplot as plt
SI_PREFIXES = {
-9: "n", # nano
-6: "µ", # micro
-3: "m", # milli
0: "", # base unit
3: "k", # kilo
6: "M", # Mega
9: "G" # Giga
}
def get_best_unit(value):
if value == 0:
return 0, ""
exponent = int(np.floor(np.log10(abs(value)) / 3) * 3)
exponent = max(min(exponent, 9), -9)
unit = SI_PREFIXES.get(exponent, "")
return exponent, unit
def format_value(value):
exponent, unit = get_best_unit(value)
return f"{value / (10**exponent):.6g} {unit}"
def calculate_histogram_data(file_path):
results = []
errors_removed = 0
total_samples = 0
try:
with open(file_path, 'r') as file:
for line in file:
if line.startswith("Index") or not line.strip():
continue
try:
_, result = line.split()
value = float(result)
total_samples += 1 # Count total samples
# Check if value is exactly 1.0000e+00
if value == 1.0:
errors_removed += 1
continue # Skip this value
results.append(value)
except ValueError:
continue
except Exception as e:
print(f"Error reading the file: {e}")
return [], 0, 0, errors_removed, total_samples
if errors_removed > 0:
print(f"ERROR: There are {errors_removed} values out of bounds (equal to 1.0), data has been removed.")
print(f"Total samples: {total_samples}, Remaining samples: {total_samples - errors_removed}")
else:
print(f"Total samples: {total_samples}")
mean = np.mean(results)
std_dev = np.std(results)
print(f"Mean: {format_value(mean)}")
print(f"Standard Deviation: {format_value(std_dev)}")
return results, mean, std_dev, errors_removed, total_samples
def create_histogram(results, mean, std_dev):
script_directory = os.path.dirname(os.path.abspath(__file__))
histogram_dir = os.path.join(script_directory, "histogram_plots")
if not os.path.exists(histogram_dir):
os.makedirs(histogram_dir)
plt.style.use('seaborn-whitegrid')
fig, ax = plt.subplots(figsize=(8, 6))
# Plot histogram
bins = 30
counts, bin_edges, _ = ax.hist(results, bins=bins, edgecolor='black', color='skyblue', alpha=0.7)
# Overlay individual data points as scatter dots
bin_centers = (bin_edges[:-1] + bin_edges[1:]) / 2
jitter = np.random.uniform(-0.1, 0.1, size=len(results)) # Adds slight randomness to prevent overlap
ax.scatter(results, np.random.uniform(0, counts.max() * 0.1, len(results)),
color='red', s=15, alpha=0.7, label=f"Mean: {format_value(mean)}\nStd Dev: {format_value(std_dev)}")
# Title and labels
ax.set_title('Histogram of Results', fontsize=16, fontweight='bold')
ax.set_xlabel('Results', fontsize=14)
ax.set_ylabel('Frequency', fontsize=14)
# Grid settings
ax.grid(True, linestyle='--', alpha=0.5)
# Set ticks for better readability
ax.tick_params(axis='both', which='major', labelsize=12)
# Save figure
histogram_path = os.path.join(histogram_dir, "histogram.png")
plt.legend()
plt.tight_layout()
plt.savefig(histogram_path, dpi=300)
print(f"Histogram saved to {histogram_path}")
plt.close()
if __name__ == "__main__":
if len(sys.argv) != 2:
print("Usage: python script.py <path_to_txt_file>")
else:
file_path = sys.argv[1]
results, mean, std_dev, errors_removed, total_samples = calculate_histogram_data(file_path)
if results:
generate_histogram = input("Do you want to create a histogram plot? (y/n): ").strip().lower()
if generate_histogram == 'y':
create_histogram(results, mean, std_dev)

BIN
modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/xschem_post_layout/testbench/statistical_calculation/histogram_plots/histogram.png Normal file
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1
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/xschemrc → modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/xschem_post_layout/testbench/xschemrc
View File

@ -15,4 +15,5 @@ source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
#### Add custom libraries (directories with .lib files)
append XSCHEM_LIBRARY_PATH :$PDK_ROOT/ihp-sg13g2/libs.tech/xschem
append XSCHEM_LIBRARY_PATH :../schematic/

20
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/output/input_pair_cm__input_pair_cm/magic_CC/input_pair_cm_MAGIC_CC_Script.tcl
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@ -1,20 +0,0 @@
# Generated by kpex 0.2.7
crashbackups stop
drc off
gds read /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/input_pair_cm.gds
load input_pair_cm
select top cell
flatten input_pair_cm_flat
load input_pair_cm_flat
cellname delete input_pair_cm -noprompt
cellname rename input_pair_cm_flat input_pair_cm
select top cell
extract path /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/output/input_pair_cm__input_pair_cm/magic_CC
extract all
ext2spice short none
ext2spice merge none
ext2spice cthresh 0.01
ext2spice subcircuits top on
ext2spice format ngspice
ext2spice -p /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/output/input_pair_cm__input_pair_cm/magic_CC -o /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/output/input_pair_cm__input_pair_cm/magic_CC/input_pair_cm.pex.spice
quit -noprompt

72
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/pex_output/input_pair_cm__input_pair_cm/magic_RC/input_pair_cm.ext
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@ -1,72 +0,0 @@
timestamp 0
version 8.3
tech ihp-sg13g2
style ngspice()
scale 1000 1 0.5
resistclasses 3000000 67000 110 88 88 88 88 18 11
parameters sg13_lv_pmos l=l w=w a1=as p1=ps a2=ad p2=pd
port "Drain2" 4 2947 3110 2985 3148 m4
port "Drain1" 3 2651 3110 2689 3148 m2
port "vdd" 1 1014 2943 1071 2995 m1
node "a_2357_3299#" 14 387.74 2357 3299 pdif 0 0 0 0 116960 6864 225960 4628 266560 4088 0 0 0 0 0 0 0 0
node "Drain2" 16 550.628 2947 3110 m4 0 0 0 0 116960 6864 32480 1584 500500 7710 245560 3788 0 0 0 0 0 0
node "a_1135_3368#" 11 3257.89 1135 3368 p 0 0 0 0 238002 7698 56404 2350 137250 3702 0 0 0 0 0 0 0 0
node "Drain1" 15 400.094 2651 3110 m2 0 0 0 0 116960 6864 278040 5372 500640 7712 0 0 0 0 0 0 0 0
node "a_1135_3839#" 11 3274.81 1135 3839 p 0 0 0 0 218514 7032 96568 3908 137250 3702 0 0 0 0 0 0 0 0
node "a_1245_3300#" 29 654.46 1245 3300 pdif 0 0 0 0 233920 13728 64960 3168 532840 8172 193480 3044 0 0 0 0 0 0
node "a_1245_3771#" 14 176.751 1245 3771 pdif 0 0 0 0 116960 6864 32480 1584 266560 4088 0 0 0 0 0 0 0 0
node "w_805_2869#" 1513432 0 805 2869 pw 223356 21272 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "vdd" 21 1653.88 1014 2943 m1 0 0 0 0 515840 19840 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUB" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cap "w_805_2869#" "a_1245_3300#" 5.4313
cap "Drain2" "a_2357_3299#" 113.693
cap "w_805_2869#" "vdd" 89.3833
cap "a_2357_3299#" "a_1245_3300#" 1001.64
cap "a_1135_3368#" "w_805_2869#" 7.96269
cap "a_1135_3839#" "Drain1" 775.115
cap "a_2357_3299#" "vdd" 683.256
cap "a_1135_3368#" "a_2357_3299#" 174.98
cap "Drain2" "a_1135_3839#" 427.559
cap "Drain2" "Drain1" 672.32
cap "a_1245_3300#" "a_1135_3839#" 170.175
cap "a_1245_3300#" "Drain1" 3329.35
cap "a_1135_3839#" "vdd" 2780.38
cap "Drain1" "vdd" 523.06
cap "w_805_2869#" "a_1245_3771#" 0.81511
cap "a_1135_3368#" "a_1135_3839#" 1458.76
cap "a_1135_3368#" "Drain1" 86.5205
cap "Drain2" "a_1245_3300#" 6266.07
cap "a_1245_3771#" "a_2357_3299#" 442.031
cap "Drain2" "vdd" 291.445
cap "a_1245_3300#" "vdd" 777.462
cap "a_1135_3368#" "Drain2" 1071.91
cap "w_805_2869#" "a_2357_3299#" 6.30488
cap "a_1135_3368#" "a_1245_3300#" 438.305
cap "a_1135_3368#" "vdd" 2791.94
cap "a_1245_3771#" "a_1135_3839#" 343.444
cap "a_1245_3771#" "Drain1" 2963.26
cap "Drain2" "a_1245_3771#" 96.2132
cap "w_805_2869#" "a_1135_3839#" 8.25481
cap "w_805_2869#" "Drain1" 8.32062
cap "a_1245_3771#" "a_1245_3300#" 646.375
cap "a_2357_3299#" "a_1135_3839#" 380.673
cap "a_2357_3299#" "Drain1" 3505.97
cap "a_1245_3771#" "vdd" 372.673
cap "w_805_2869#" "Drain2" 6.1761
cap "a_1135_3368#" "a_1245_3771#" 107.634
device msubckt sg13_lv_pmos 2357 3367 2358 3368 l=40 w=800 "vdd" "a_1135_3839#" 80 0 "a_2357_3299#" 800 54400,1736 "Drain1" 800 30400,876
device msubckt sg13_lv_pmos 2357 3483 2358 3484 l=40 w=800 "vdd" "a_1135_3839#" 80 0 "Drain1" 800 30400,876 "a_2357_3299#" 800 54400,1736
device msubckt sg13_lv_pmos 1245 3368 1246 3369 l=40 w=800 "vdd" "a_1135_3368#" 80 0 "a_1245_3300#" 800 54400,1736 "Drain2" 800 30400,876
device msubckt sg13_lv_pmos 1245 3484 1246 3485 l=40 w=800 "vdd" "a_1135_3368#" 80 0 "Drain2" 800 30400,876 "a_1245_3300#" 800 54400,1736
device msubckt sg13_lv_pmos 2357 3838 2358 3839 l=40 w=800 "vdd" "a_1135_3368#" 80 0 "a_1245_3300#" 800 54400,1736 "Drain2" 800 30400,876
device msubckt sg13_lv_pmos 2357 3954 2358 3955 l=40 w=800 "vdd" "a_1135_3368#" 80 0 "Drain2" 800 30400,876 "a_1245_3300#" 800 54400,1736
device msubckt sg13_lv_pmos 1245 3839 1246 3840 l=40 w=800 "vdd" "a_1135_3839#" 80 0 "a_1245_3771#" 800 54400,1736 "Drain1" 800 30400,876
device msubckt sg13_lv_pmos 1245 3955 1246 3956 l=40 w=800 "vdd" "a_1135_3839#" 80 0 "Drain1" 800 30400,876 "a_1245_3771#" 800 54400,1736
device msubckt sg13_lv_pmos 2357 4309 2358 4310 l=40 w=800 "vdd" "a_1135_3839#" 80 0 "a_2357_3299#" 800 54400,1736 "Drain1" 800 30400,876
device msubckt sg13_lv_pmos 2357 4425 2358 4426 l=40 w=800 "vdd" "a_1135_3839#" 80 0 "Drain1" 800 30400,876 "a_2357_3299#" 800 54400,1736
device msubckt sg13_lv_pmos 1245 4310 1246 4311 l=40 w=800 "vdd" "a_1135_3368#" 80 0 "a_1245_3300#" 800 54400,1736 "Drain2" 800 30400,876
device msubckt sg13_lv_pmos 1245 4426 1246 4427 l=40 w=800 "vdd" "a_1135_3368#" 80 0 "Drain2" 800 30400,876 "a_1245_3300#" 800 54400,1736
device msubckt sg13_lv_pmos 2357 4780 2358 4781 l=40 w=800 "vdd" "a_1135_3368#" 80 0 "a_1245_3300#" 800 54400,1736 "Drain2" 800 30400,876
device msubckt sg13_lv_pmos 2357 4896 2358 4897 l=40 w=800 "vdd" "a_1135_3368#" 80 0 "Drain2" 800 30400,876 "a_1245_3300#" 800 54400,1736
device msubckt sg13_lv_pmos 1245 4781 1246 4782 l=40 w=800 "vdd" "a_1135_3839#" 80 0 "a_1245_3771#" 800 54400,1736 "Drain1" 800 30400,876
device msubckt sg13_lv_pmos 1245 4897 1246 4898 l=40 w=800 "vdd" "a_1135_3839#" 80 0 "Drain1" 800 30400,876 "a_1245_3771#" 800 54400,1736

4
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/pex_output/input_pair_cm__input_pair_cm/magic_RC/input_pair_cm.res.ext
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@ -1,4 +0,0 @@
scale 1000 1 0.5
rnode "Drain2" 0 0 2947 3110 0
rnode "Drain1" 0 0 2651 3110 0
rnode "vdd" 0 0 1014 2943 0

27
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/pex_output/input_pair_cm__input_pair_cm/magic_RC/input_pair_cm_MAGIC_RC_Script.tcl
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@ -1,27 +0,0 @@
# Generated by kpex 0.2.7
crashbackups stop
drc off
gds read /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/input_pair_cm.gds
load input_pair_cm
select top cell
flatten input_pair_cm_flat
load input_pair_cm_flat
cellname delete input_pair_cm -noprompt
cellname rename input_pair_cm_flat input_pair_cm
select top cell
extract path /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/pex_output/input_pair_cm__input_pair_cm/magic_RC
extract do resistance
extract all
ext2sim labels on
ext2sim
extresist tolerance 1
extresist all
ext2spice short resistor
ext2spice merge conservative
ext2spice cthresh 0.02
ext2spice rthresh 50
ext2spice extresist on
ext2spice subcircuits top on
ext2spice format ngspice
ext2spice -p /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/pex_output/input_pair_cm__input_pair_cm/magic_RC -o /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/pex_output/input_pair_cm__input_pair_cm/magic_RC/input_pair_cm.pex.spice
quit -noprompt

BIN
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/pex_output/input_pair_cm__input_pair_cm/magic_RC/input_pair_cm_MAGIC_report.rdb.gz
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19
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/run_kpex.sh
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@ -1,19 +0,0 @@
#!/bin/bash
source /home/pedersen/misc/klayout_pex/bin/activate
export KPEX_MAGIC_EXE="$HOME/.local/bin/magic"
echo "KPEX_MAGIC_EXE is: $KPEX_MAGIC_EXE"
kpex \
--pdk ihp_sg13g2 \
--magic \
--gds input_pair_cm.gds \
--schematic schematic_mod/simulations/input_pair_cm.spice \
--cell input_pair_cm \
--magicrc /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/magic/ihp-sg13g2.magicrc\
--magic_mode RC \
--magic_cthresh 0.02 \
--magic_rthresh 50 \
--magic_short resistor \
--magic_merge conservative \
--out_dir ./pex_output

58
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/xschem/input_pair_cm.sch
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@ -1,58 +0,0 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 490 -650 490 -600 {
lab=#net1}
N 810 -650 810 -600 {
lab=#net1}
N 810 -540 810 -470 {
lab=Drain2}
N 650 -650 810 -650 {
lab=#net1}
N 650 -710 650 -650 {
lab=#net1}
N 490 -650 650 -650 {
lab=#net1}
N 650 -570 810 -570 {
lab=#net2}
N 490 -540 490 -470 {
lab=Drain1}
N 440 -570 450 -570 {
lab=v+}
N 850 -570 860 -570 {
lab=v-}
N 650 -570 650 -550 {lab=#net2}
N 490 -570 650 -570 {
lab=#net2}
N 650 -490 650 -470 {lab=#net3}
C {ipin.sym} 440 -570 0 0 {name=p3 lab=v+}
C {ipin.sym} 860 -570 0 1 {name=p4 lab=v-}
C {sg13g2_pr/sg13_lv_pmos.sym} 470 -570 0 0 {name=M2
l=200n
w=32u
ng=4
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 830 -570 0 1 {name=M1
l=200n
w=32u
ng=4
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/ntap1.sym} 650 -520 0 0 {name=R1
model=ntap1
spiceprefix=X
w=0.78e-6
l=0.78e-6
}
C {iopin.sym} 810 -470 0 0 {name=p7 lab=Drain2}
C {iopin.sym} 490 -470 0 0 {name=p1 lab=Drain1}
C {iopin.sym} 650 -470 0 0 {name=p2 lab=vdd}
C {iopin.sym} 650 -710 0 0 {name=p5 lab=top}

26
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/xschem/input_pair_cm.sym
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@ -1,26 +0,0 @@
v {xschem version=3.4.6 file_version=1.2}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
T {@symname} -76.5 -6 0 0 0.3 0.3 {}
T {@name} 135 -52 0 0 0.2 0.2 {}
P 4 5 130 -40 -130 -40 -130 40 130 40 130 -40 {}
B 5 147.5 -32.5 152.5 -27.5 {name=top dir=inout}
L 7 130 -30 150 -30 {}
T {top} 125 -34 0 1 0.2 0.2 {}
B 5 -152.5 -32.5 -147.5 -27.5 {name=v+ dir=in}
L 4 -150 -30 -130 -30 {}
T {v+} -125 -34 0 0 0.2 0.2 {}
B 5 -152.5 -12.5 -147.5 -7.5 {name=v- dir=in}
L 4 -150 -10 -130 -10 {}
T {v-} -125 -14 0 0 0.2 0.2 {}
B 5 147.5 -12.5 152.5 -7.5 {name=vdd dir=inout}
L 7 130 -10 150 -10 {}
T {vdd} 125 -14 0 1 0.2 0.2 {}
B 5 147.5 7.5 152.5 12.5 {name=Drain1 dir=inout}
L 7 130 10 150 10 {}
T {Drain1} 125 6 0 1 0.2 0.2 {}
B 5 147.5 27.5 152.5 32.5 {name=Drain2 dir=inout}
L 7 130 30 150 30 {}
T {Drain2} 125 26 0 1 0.2 0.2 {}

BIN
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/misc/cross_con.gds
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modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/misc/cross_con_new.gds
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modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/macros/gallery.gds
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50
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/inverter.sch
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@ -1,50 +0,0 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 330 -280 370 -280 {lab=Vin}
N 330 -280 330 -190 {lab=Vin}
N 330 -190 370 -190 {lab=Vin}
N 410 -230 490 -230 {lab=Vout}
N 410 -230 410 -220 {lab=Vout}
N 410 -250 410 -230 {lab=Vout}
N 410 -160 410 -130 {lab=Gnd}
N 410 -340 410 -310 {lab=Vdd}
N 410 -280 520 -280 {lab=#net1}
N 410 -340 520 -340 {lab=Vdd}
N 410 -190 520 -190 {lab=#net2}
N 410 -130 520 -130 {lab=Gnd}
C {sg13g2_pr/sg13_lv_nmos.sym} 390 -190 2 1 {name=M1
l=0.45u
w=1.0u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 390 -280 0 0 {name=M2
l=0.45u
w=2.0u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {iopin.sym} 490 -230 2 1 {name=p2 lab=Vout}
C {iopin.sym} 410 -340 2 0 {name=p5 lab=Vdd}
C {iopin.sym} 330 -240 2 0 {name=p6 lab=Vin}
C {iopin.sym} 410 -130 2 0 {name=p1 lab=Gnd}
C {sg13g2_pr/ntap1.sym} 520 -310 0 0 {name=R1
model=ntap1
spiceprefix=X
w=0.78e-6
l=0.78e-6
}
C {sg13g2_pr/ptap1.sym} 520 -160 2 1 {name=R2
model=ptap1
spiceprefix=X
w=0.78e-6
l=0.78e-6
}

25
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/inverter.sym
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@ -1,25 +0,0 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 7 -70 -80 -70 -60 {}
L 7 -150 0 -130 0 {}
L 7 110 0 130 0 {}
L 7 -70 70 -70 90 {}
B 5 -72.5 -82.5 -67.5 -77.5 {name=Vdd dir=inout}
B 5 -152.5 -2.5 -147.5 2.5 {name=Vin dir=inout}
B 5 127.5 -2.5 132.5 2.5 {name=Vout dir=inout}
B 5 -72.5 87.5 -67.5 92.5 {name=Gnd dir=inout}
A 4 105 0 7.071067811865476 135 360 {}
P 4 5 100 0 -130 -80 -130 90 100 0 100 0 {}
T {@symname} -84 -6 0 0 0.3 0.3 {}
T {@name} -45 -32 0 0 0.2 0.2 {}
T {Vdd} -74 -55 3 1 0.2 0.2 {}
T {Vin} -125 -4 0 0 0.2 0.2 {}
T {Vout} 80 -9 0 1 0.2 0.2 {}
T {Gnd} -66 65 1 1 0.2 0.2 {}

68
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/inverter_tb.sch
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@ -1,68 +0,0 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
B 2 710 -550 1510 -150 {flags=graph
y1=-0.0023
y2=1.3
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=2e-06
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
node=vout
color=4
dataset=-1
unitx=1
logx=0
logy=0
}
N 150 -170 150 -140 {lab=Vin}
N 70 -170 70 -140 {lab=Vdd}
N 70 -80 70 -60 {lab=GND}
N 110 -60 150 -60 {lab=GND}
N 150 -80 150 -60 {lab=GND}
N 110 -60 110 -50 {lab=GND}
N 70 -60 110 -60 {lab=GND}
N 320 -410 320 -380 {lab=Vdd}
N 320 -210 320 -190 {lab=GND}
N 220 -300 240 -300 {lab=Vin}
N 520 -300 540 -300 {lab=Vout}
C {vsource.sym} 150 -110 0 0 {name=V1 value="PULSE(0 1.2 0.5u 10n 10n 1u 2u 1)" savecurrent=false}
C {vsource.sym} 70 -110 0 0 {name=V2 value=1.2 savecurrent=false}
C {gnd.sym} 110 -50 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 150 -170 0 0 {name=p1 sig_type=std_logic lab=Vin}
C {lab_pin.sym} 70 -170 0 0 {name=p3 sig_type=std_logic lab=Vdd}
C {code_shown.sym} 40 -540 0 0 {name=NGSPICE
only_toplevel=true
value="
.control
save all
tran 50n 2u
write test_inverter.raw
.endc
" }
C {devices/code_shown.sym} 280 -540 0 0 {name=MODEL only_toplevel=true
format="tcleval( @value )"
value="
.lib cornerMOSlv.lib mos_tt
.lib cornerRES.lib res_typ
"}
C {launcher.sym} 770 -120 0 0 {name=h5
descr="load waves"
tclcommand="xschem raw_read $netlist_dir/test_inverter.raw tran"
}
C {inverter.sym} 390 -300 0 0 {name=x1}
C {lab_pin.sym} 220 -300 0 0 {name=p2 sig_type=std_logic lab=Vin}
C {gnd.sym} 320 -190 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 320 -410 0 0 {name=p4 sig_type=std_logic lab=Vdd}
C {lab_pin.sym} 540 -300 0 1 {name=p5 sig_type=std_logic lab=Vout}

BIN
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/layout/inverter.gds
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10
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/layout/inverter_extracted.cir
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@ -1,10 +0,0 @@
* Extracted by KLayout with SG13G2 LVS runset on : 07/07/2025 16:12
.SUBCKT inverter Gnd Vout Vin Vdd
M$1 Gnd Vin Vout \$1 sg13_lv_nmos L=0.45u W=1u AS=0.34p AD=0.34p PS=2.68u
+ PD=2.68u
M$2 Vdd Vin Vout \$2 sg13_lv_pmos L=0.45u W=2u AS=0.68p AD=0.68p PS=4.68u
+ PD=4.68u
R$3 \$2 Vdd ntap1 A=0.6084p P=3.12u
R$4 \$1 Gnd ptap1 A=0.6084p P=3.12u
.ENDS inverter

0
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/inverter.nodes
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0
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/inverter.sim
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58
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/kpex.log
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@ -1,58 +0,0 @@
[2025-07-09 12:17:50,912] [INFO] GDS input file passed, running in LVS mode
[2025-07-09 12:17:50,914] [INFO] Found cell inverter in GDS ../layout/inverter.gds (only top cell)
[2025-07-09 12:17:50,920] [INFO] Calling MAGIC
[2025-07-09 12:17:50,921] [SUBPROCESS] magic -dnull -noconsole -rcfile /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/magic/ihp-sg13g2.magicrc ./pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl, output file: ./pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Output.txt
[2025-07-09 12:17:50,939] [SUBPROCESS]
[2025-07-09 12:17:50,940] [SUBPROCESS] Magic 8.3 revision 530 - Compiled on Mo 7. Jul 14:09:23 CEST 2025.
[2025-07-09 12:17:50,941] [SUBPROCESS] Starting magic under Tcl interpreter
[2025-07-09 12:17:50,942] [SUBPROCESS] Using the terminal as the console.
[2025-07-09 12:17:50,942] [SUBPROCESS] Using NULL graphics device.
[2025-07-09 12:17:50,974] [SUBPROCESS] Processing system .magicrc file
[2025-07-09 12:17:50,981] [SUBPROCESS] Sourcing design .magicrc for technology ihp-sg13g2 ...
[2025-07-09 12:17:50,982] [SUBPROCESS] 2 Magic internal units = 1 Lambda
[2025-07-09 12:17:51,003] [SUBPROCESS] Input style sg13g2(): scaleFactor=2, multiplier=2
[2025-07-09 12:17:51,101] [SUBPROCESS] The following types are not handled by extraction and will be treated as non-electrical types:
[2025-07-09 12:17:51,102] [SUBPROCESS] fillfet sealcont difffill nemitter hvnemitter hvisodiffres sealvia1 sealvia2 sealvia3 sealvia4 sealvia5 sealvia6 pad seal thruvia
[2025-07-09 12:17:51,105] [SUBPROCESS] Scaled tech values by 2 / 1 to match internal grid scaling
[2025-07-09 12:17:51,106] [SUBPROCESS] Loading "./pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl" from command line.
[2025-07-09 12:17:51,106] [SUBPROCESS] Warning: Calma reading is not undoable! I hope that's OK.
[2025-07-09 12:17:51,107] [SUBPROCESS] Library written using GDS-II Release 6.0
[2025-07-09 12:17:51,108] [SUBPROCESS] Library name: LIB
[2025-07-09 12:17:51,108] [SUBPROCESS] Reading "$$$CONTEXT_INFO$$$".
[2025-07-09 12:17:51,108] [SUBPROCESS] Reading "nmos".
[2025-07-09 12:17:51,109] [SUBPROCESS] Reading "ptap1".
[2025-07-09 12:17:51,109] [SUBPROCESS] Making label "sub!" on type isosubstrate in cell ptap1 sticky.
[2025-07-09 12:17:51,110] [SUBPROCESS] Reading "ntap1".
[2025-07-09 12:17:51,110] [SUBPROCESS] Reading "pmos$1".
[2025-07-09 12:17:51,111] [SUBPROCESS] Reading "inverter".
[2025-07-09 12:17:51,113] [SUBPROCESS] Extracting inverter into /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter.ext:
[2025-07-09 12:17:51,114] [SUBPROCESS] Port: name = Vout is new node 0x6202078064b0
[2025-07-09 12:17:51,114] [SUBPROCESS] Location is (266, -211); drivepoint (266, -211)
[2025-07-09 12:17:51,115] [SUBPROCESS] Port: name = Vin is new node 0x62020780a810
[2025-07-09 12:17:51,116] [SUBPROCESS] Location is (95, -213); drivepoint (95, -213)
[2025-07-09 12:17:51,116] [SUBPROCESS] Port: name = Gnd is new node 0x6202079978f0
[2025-07-09 12:17:51,117] [SUBPROCESS] Location is (20, -732); drivepoint (20, -732)
[2025-07-09 12:17:51,117] [SUBPROCESS] Port: name = Vdd is new node 0x62020818bf70
[2025-07-09 12:17:51,118] [SUBPROCESS] Location is (-205, 318); drivepoint (-205, 318)
[2025-07-09 12:17:51,118] [SUBPROCESS] Total Nets: 4
[2025-07-09 12:17:51,119] [SUBPROCESS] Nets extracted: 4 (1.000000)
[2025-07-09 12:17:51,119] [SUBPROCESS] Nets output: 4 (1.000000)
[2025-07-09 12:17:51,120] [SUBPROCESS] Devs merged: 0
[2025-07-09 12:17:51,120] [SUBPROCESS] exttospice finished.
[2025-07-09 12:17:51,121] [INFO] MAGIC succeeded after 0.1993s
[2025-07-09 12:17:51,127] [SUBPROCESS] Report DB saved at: ./pex_output/inverter__inverter/magic_RC/inverter_MAGIC_report.rdb.gz
[2025-07-09 12:17:51,128] [SUBPROCESS] SPICE netlist saved at: ./pex_output/inverter__inverter/magic_RC/inverter.pex.spice
[2025-07-09 12:17:51,129] [SUBPROCESS] * NGSPICE file created from inverter.ext - technology: ihp-sg13g2
.subckt inverter Vout Vin Gnd Vdd
X0 Vout Vin Vdd Vdd sg13_lv_pmos ad=0.68p pd=4.68u as=0.68p ps=4.68u w=2u l=0.45u
X1 Vout Vin Gnd Gnd sg13_lv_nmos ad=0.34p pd=2.68u as=0.34p ps=2.68u w=1u l=0.45u
C0 Vdd Vin 0.14482f
C1 Vout Vdd 0.13155f
C2 Vout Vin 0.10077f
R0 Vin Vin.n0 7.52248
C3 Vout Gnd 0.39245f
C4 Vin Gnd 0.64666f
C5 Vdd Gnd 0.15308f
.ends

58
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/kpex_plain.log
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@ -1,58 +0,0 @@
GDS input file passed, running in LVS mode
Found cell inverter in GDS ../layout/inverter.gds (only top cell)
Calling MAGIC
magic -dnull -noconsole -rcfile /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/magic/ihp-sg13g2.magicrc ./pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl, output file: ./pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Output.txt
Magic 8.3 revision 530 - Compiled on Mo 7. Jul 14:09:23 CEST 2025.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology ihp-sg13g2 ...
2 Magic internal units = 1 Lambda
Input style sg13g2(): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
fillfet sealcont difffill nemitter hvnemitter hvisodiffres sealvia1 sealvia2 sealvia3 sealvia4 sealvia5 sealvia6 pad seal thruvia
Scaled tech values by 2 / 1 to match internal grid scaling
Loading "./pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl" from command line.
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "$$$CONTEXT_INFO$$$".
Reading "nmos".
Reading "ptap1".
Making label "sub!" on type isosubstrate in cell ptap1 sticky.
Reading "ntap1".
Reading "pmos$1".
Reading "inverter".
Extracting inverter into /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter.ext:
Port: name = Vout is new node 0x6202078064b0
Location is (266, -211); drivepoint (266, -211)
Port: name = Vin is new node 0x62020780a810
Location is (95, -213); drivepoint (95, -213)
Port: name = Gnd is new node 0x6202079978f0
Location is (20, -732); drivepoint (20, -732)
Port: name = Vdd is new node 0x62020818bf70
Location is (-205, 318); drivepoint (-205, 318)
Total Nets: 4
Nets extracted: 4 (1.000000)
Nets output: 4 (1.000000)
Devs merged: 0
exttospice finished.
MAGIC succeeded after 0.1993s
Report DB saved at: ./pex_output/inverter__inverter/magic_RC/inverter_MAGIC_report.rdb.gz
SPICE netlist saved at: ./pex_output/inverter__inverter/magic_RC/inverter.pex.spice
* NGSPICE file created from inverter.ext - technology: ihp-sg13g2
.subckt inverter Vout Vin Gnd Vdd
X0 Vout Vin Vdd Vdd sg13_lv_pmos ad=0.68p pd=4.68u as=0.68p ps=4.68u w=2u l=0.45u
X1 Vout Vin Gnd Gnd sg13_lv_nmos ad=0.34p pd=2.68u as=0.34p ps=2.68u w=1u l=0.45u
C0 Vdd Vin 0.14482f
C1 Vout Vdd 0.13155f
C2 Vout Vin 0.10077f
R0 Vin Vin.n0 7.52248
C3 Vout Gnd 0.39245f
C4 Vin Gnd 0.64666f
C5 Vdd Gnd 0.15308f
.ends

23
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter.ext
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@ -1,23 +0,0 @@
timestamp 0
version 8.3
tech ihp-sg13g2
style ngspice()
scale 1000 1 0.5
resistclasses 3000000 67000 110 88 88 88 88 18 11
parameters sg13_lv_nmos l=l w=w a1=as p1=ps a2=ad p2=pd
parameters sg13_lv_pmos l=l w=w a1=as p1=ps a2=ad p2=pd
port "Vout" 2 266 -211 298 -173 m1
port "Vin" 3 95 -213 127 -175 m1
port "Vdd" 5 -205 318 -173 356 m1
port "Gnd" 4 20 -732 52 -694 m1
node "ptap1_0.sub!" 0 0 28 -796 isosub 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "Vout" 1 392.446 266 -211 m1 0 0 0 0 91916 2354 0 0 0 0 0 0 0 0 0 0 0 0
node "Vin" 0 646.659 95 -213 m1 0 0 0 0 13590 482 0 0 0 0 0 0 0 0 0 0 0 0
node "Vdd" 1 153.076 -205 318 m1 0 0 0 0 42800 1364 0 0 0 0 0 0 0 0 0 0 0 0
equiv "Vdd" "ntap1_0.well"
substrate "Gnd" 0 0 20 -732 m1 0 0 0 0 21536 1036 0 0 0 0 0 0 0 0 0 0 0 0
cap "Vdd" "Vin" 144.819
cap "Vdd" "Vout" 131.55
cap "Vout" "Vin" 100.772
device msubckt sg13_lv_nmos 67 -562 68 -561 l=90 w=200 "Gnd" "Vin" 180 0 "Gnd" 200 13600,536 "Vout" 200 13600,536
device msubckt sg13_lv_pmos 67 9 68 10 l=90 w=400 "Vdd" "Vin" 180 0 "Vdd" 400 27200,936 "Vout" 400 27200,936

9
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter.res.ext
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@ -1,9 +0,0 @@
scale 1000 1 0.5
rnode "Vdd" 0 -0 -205 318 0
rnode "ntap1_0.well" 0 0 -63 345 0
resist "ntap1_0.well" "Vdd" 8.51657
rnode "Gnd" 0 0 20 -732 0
rnode "Vin.n0" 0 0 111 -158 0
rnode "Vin" 0 0 95 -213 0
resist "Vin" "Vin.n0" 7.52198
rnode "Vout" 0 0 266 -211 0

27
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl
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@ -1,27 +0,0 @@
# Generated by kpex 0.2.7
crashbackups stop
drc off
gds read /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/layout/inverter.gds
load inverter
select top cell
flatten inverter_flat
load inverter_flat
cellname delete inverter -noprompt
cellname rename inverter_flat inverter
select top cell
extract path /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/magic_RC
extract do resistance
extract all
ext2sim labels on
ext2sim
extresist tolerance 1
extresist all
ext2spice short resistor
ext2spice merge conservative
ext2spice cthresh 0.02
ext2spice rthresh 50
ext2spice extresist on
ext2spice subcircuits top on
ext2spice format ngspice
ext2spice -p /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/magic_RC -o /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter.pex.spice
quit -noprompt

BIN
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter_MAGIC_report.rdb.gz
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Binary file not shown.

61
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/scripts/match_subckt_order.py
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import sys
import re
from pathlib import Path
def get_original_io_order(original_netlist_path):
io_pins = []
with open(original_netlist_path, "r") as f:
for line in f:
stripped = line.strip()
# Look for .subckt line (not commented out)
if stripped.startswith(".subckt"):
tokens = stripped.split()
# tokens[0] = '.subckt', tokens[1] = subckt name, rest are pins
if len(tokens) >= 3:
io_pins = tokens[2:]
break
if not io_pins:
raise ValueError("Could not find IO pins in original schematic")
return io_pins
def reorder_pex_subckt(pex_path, correct_order):
with open(pex_path, "r") as f:
lines = f.readlines()
new_lines = []
subckt_found = False
for line in lines:
if line.strip().startswith(".subckt") and not subckt_found:
tokens = line.strip().split()
subckt_name = tokens[1]
ports = tokens[2:]
if set(ports) != set(correct_order):
raise ValueError("Port names in PEX netlist don't match original IO pins")
# Create new subckt line with reordered ports
reordered_line = ".subckt " + subckt_name +"_pex"+" " + " ".join(correct_order) + "\n"
new_lines.append(reordered_line)
subckt_found = True
else:
new_lines.append(line)
with open(pex_path, "w") as f:
f.writelines(new_lines)
print(f"Rewrote subckt line in {pex_path}")
if __name__ == "__main__":
if len(sys.argv) != 3:
print("Usage: python patch_pex_order.py <pex_spice_path> <original_schematic_spice_path>")
sys.exit(1)
pex_spice = Path(sys.argv[1])
original_schematic = Path(sys.argv[2])
io_order = get_original_io_order(original_schematic)
reorder_pex_subckt(pex_spice, io_order)

84
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/xschem/inverter_tb_pex.sch
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@ -1,84 +0,0 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
B 2 710 -550 1510 -150 {flags=graph
y1=-0.0023
y2=1.3
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=2e-06
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
node=vout
color=4
dataset=-1
unitx=1
logx=0
logy=0
}
N 150 -170 150 -140 {lab=Vin}
N 70 -170 70 -140 {lab=Vdd}
N 70 -80 70 -60 {lab=GND}
N 110 -60 150 -60 {lab=GND}
N 150 -80 150 -60 {lab=GND}
N 110 -60 110 -50 {lab=GND}
N 70 -60 110 -60 {lab=GND}
N 320 -410 320 -380 {lab=Vdd}
N 320 -210 320 -190 {lab=GND}
N 220 -300 240 -300 {lab=Vin}
N 520 -300 540 -300 {lab=Vout}
C {vsource.sym} 150 -110 0 0 {name=V1 value="PULSE(0 1.2 0.5u 10n 10n 1u 2u 1)" savecurrent=false}
C {vsource.sym} 70 -110 0 0 {name=V2 value=1.2 savecurrent=false}
C {gnd.sym} 110 -50 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 150 -170 0 0 {name=p1 sig_type=std_logic lab=Vin}
C {lab_pin.sym} 70 -170 0 0 {name=p3 sig_type=std_logic lab=Vdd}
C {code_shown.sym} 40 -540 0 0 {name=NGSPICE
only_toplevel=true
value="
.control
save all
tran 50n 2u
write test_inverter.raw
.endc
" }
C {devices/code_shown.sym} 280 -540 0 0 {name=MODEL only_toplevel=true
format="tcleval( @value )"
value="
.lib cornerMOSlv.lib mos_tt
.lib cornerRES.lib res_typ
"}
C {launcher.sym} 770 -120 0 0 {name=h5
descr="load waves"
tclcommand="xschem raw_read $netlist_dir/test_inverter.raw tran"
}
C {inverter.sym} 390 -300 0 0 {
name=x1
schematic=inverter_pex
spice_sym_def="
.subckt inverter_pex Vdd Vin Vout Gnd
X0 Vout Vin Vdd Vdd sg13_lv_pmos ad=0.68p pd=4.68u as=0.68p ps=4.68u w=2u l=0.45u
X1 Vout Vin Gnd Gnd sg13_lv_nmos ad=0.34p pd=2.68u as=0.34p ps=2.68u w=1u l=0.45u
C0 Vdd Vin 0.14482f
C1 Vout Vdd 0.13155f
C2 Vout Vin 0.10077f
R0 Vin Vin.n0 7.52248
C3 Vout Gnd 0.39245f
C4 Vin Gnd 0.64666f
C5 Vdd Gnd 0.15308f
.ends
"
}
C {lab_pin.sym} 220 -300 0 0 {name=p2 sig_type=std_logic lab=Vin}
C {gnd.sym} 320 -190 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 320 -410 0 0 {name=p4 sig_type=std_logic lab=Vdd}
C {lab_pin.sym} 540 -300 0 1 {name=p5 sig_type=std_logic lab=Vout}

12
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/xschem/xschemrc
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# xschemrc - Custom configuration file for xschem
# This file sources another xschemrc file from a known location
# Source the base configuration from a known location
source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
# (Optional) Add any custom overrides or extensions below
# set xschem_library_path /home/user/my_libs
# set xschem_gui_font "Monospace 10"
append XSCHEM_LIBRARY_PATH :$PDK_ROOT/ihp-sg13g2/libs.tech/xschem
append XSCHEM_LIBRARY_PATH :../../