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This commit is contained in:
PhillipRambo 2025-07-25 16:33:53 +02:00
parent 28f46213dd
commit 18b21b1d4d
47 changed files with 17090 additions and 1360 deletions
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4
modules/module_0_foundations/sg13_nmos_lv.py
View File

@ -43,8 +43,8 @@ ngspice = NgspiceSimulator(
nmos_sweep = TransistorSweep(
mos_type="nmos",
vgs=(0, 1.2, 0.01),
vds=(0, 1.2, 0.01),
vgs=(0, 1.2, 0.1),
vds=(0, 1.2, 0.1),
vbs=(0, -1.2, -0.1),
length = [130e-9, 260e-9, 390e-9, 520e-9, 650e-9, 780e-9, 910e-9, 1040e-9, 1170e-9, 1300e-9, 1430e-9, 1560e-9, 1690e-9, 1820e-9, 1950e-9, 2080e-9, 2210e-9, 2340e-9, 2470e-9, 2600e-9, 2730e-9, 2860e-9, 2990e-9, 3120e-9, 3250e-9, 3380e-9, 3510e-9, 3640e-9, 3770e-9, 3900e-9, 4030e-9, 4160e-9, 4290e-9, 4420e-9, 4550e-9, 4680e-9, 4810e-9, 4940e-9, 5070e-9, 5200e-9, 5330e-9, 5460e-9, 5590e-9, 5720e-9, 5850e-9, 5980e-9, 6110e-9, 6240e-9, 6370e-9, 6500e-9, 6630e-9, 6760e-9, 6890e-9, 7020e-9, 7150e-9, 7280e-9, 7410e-9, 7540e-9, 7670e-9, 7800e-9, 7930e-9, 8060e-9, 8190e-9, 8320e-9, 8450e-9, 8580e-9, 8710e-9, 8840e-9, 8970e-9, 9100e-9, 9230e-9, 9360e-9, 9490e-9, 9620e-9, 9750e-9, 9880e-9]
)

4
modules/module_1_bandgap_reference/part_1_OTA/testbenches/ota_testbench_mc_mis.sch
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@ -70,12 +70,12 @@ C {devices/code_shown.sym} 25 -1260 0 0 {name=NGSPICE only_toplevel=false
value="
.control
let run = 1
let mc_runs = 100
let mc_runs = 10
set curplot = new
set scratch = $curplot
dowhile run <= mc_runs
reset
dc temp 0 70 5
dc temp 70 0 5
set run = $&run
set dc = $curplot
setplot $scratch

508
modules/module_1_bandgap_reference/part_3_layout/BGR_layout/final_bandgapreference/sg13g2_minimal.lyrdb Normal file
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@ -0,0 +1,508 @@
<?xml version="1.0" encoding="utf-8"?>
<report-database>
<description>design rules: sg13g2_minimal | layout cell: full_bandgap</description>
<original-file>full_bandgap_layout_pads.gds</original-file>
<generator>drc: script='/home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_minimal.lydrc'</generator>
<top-cell>full_bandgap</top-cell>
<tags>
<tag>
<name>waived</name>
<description/>
</tag>
<tag>
<name>red</name>
<description/>
</tag>
<tag>
<name>green</name>
<description/>
</tag>
<tag>
<name>blue</name>
<description/>
</tag>
<tag>
<name>yellow</name>
<description/>
</tag>
<tag>
<name>important</name>
<description/>
</tag>
</tags>
<categories>
<category>
<name>Act.a</name>
<description>Min. Activ width = 0.15</description>
<categories>
</categories>
</category>
<category>
<name>Act.b</name>
<description>Min. Activ space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>AFil.g/g1</name>
<description>Global Activ density [%] = 35.00 .. 55.00</description>
<categories>
</categories>
</category>
<category>
<name>AFil.g2/g3</name>
<description>Activ coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 65.00</description>
<categories>
</categories>
</category>
<category>
<name>TGO.f</name>
<description>Min. ThickGateOx width = 0.86</description>
<categories>
</categories>
</category>
<category>
<name>Gat.a</name>
<description>Min. GatPoly width = 0.13</description>
<categories>
</categories>
</category>
<category>
<name>Gat.b</name>
<description>Min. GatPoly space or notch = 0.18</description>
<categories>
</categories>
</category>
<category>
<name>Gat.d</name>
<description>Min. GatPoly space to Activ = 0.07</description>
<categories>
</categories>
</category>
<category>
<name>GFil.g</name>
<description>Min. global GatPoly density [%] = 15.00</description>
<categories>
</categories>
</category>
<category>
<name>Cnt.a</name>
<description>Min. and max. Cont width = 0.16</description>
<categories>
</categories>
</category>
<category>
<name>Cnt.b</name>
<description>Min. Cont space = 0.18</description>
<categories>
</categories>
</category>
<category>
<name>M1.a</name>
<description>Min. Metal1 width = 0.16</description>
<categories>
</categories>
</category>
<category>
<name>M1.b</name>
<description>Min. Metal1 space or notch = 0.18</description>
<categories>
</categories>
</category>
<category>
<name>M1.j/k</name>
<description>Global Metal1 density [%] = 35.0 .. 60.0</description>
<categories>
</categories>
</category>
<category>
<name>M2.a</name>
<description>Min. Metal2 width = 0.20</description>
<categories>
</categories>
</category>
<category>
<name>M2.b</name>
<description>Min. Metal2 space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>M2.j/k</name>
<description>Global Metal2 density [%] = 35.00 .. 60.00</description>
<categories>
</categories>
</category>
<category>
<name>M3.a</name>
<description>Min. Metal3 width = 0.20</description>
<categories>
</categories>
</category>
<category>
<name>M3.b</name>
<description>Min. Metal3 space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>M3.j/k</name>
<description>Global Metal3 density [%] = 35.00 .. 60.00</description>
<categories>
</categories>
</category>
<category>
<name>M4.a</name>
<description>Min. Metal4 width = 0.20</description>
<categories>
</categories>
</category>
<category>
<name>M4.b</name>
<description>Min. Metal4 space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>M4.j/k</name>
<description>Global Metal4 density [%] = 35.00 .. 60.00</description>
<categories>
</categories>
</category>
<category>
<name>M5.a</name>
<description>Min. Metal5 width = 0.20</description>
<categories>
</categories>
</category>
<category>
<name>M5.b</name>
<description>Min. Metal5 space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>M5.j/k</name>
<description>Global Metal5 density [%] = 35.00 .. 60.00</description>
<categories>
</categories>
</category>
<category>
<name>M1Fil.h/k</name>
<description>Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>M2Fil.h/k</name>
<description>Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>M3Fil.h/k</name>
<description>Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>M4Fil.h/k</name>
<description>Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>M5Fil.h/k</name>
<description>Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>V1.a</name>
<description>Min. and max. Via1 width = 0.19</description>
<categories>
</categories>
</category>
<category>
<name>V1.b</name>
<description>Min. Via1 space = 0.22</description>
<categories>
</categories>
</category>
<category>
<name>V2.a</name>
<description>Min. and max. Via2 width = 0.19</description>
<categories>
</categories>
</category>
<category>
<name>V2.b</name>
<description>Min. Via2 space = 0.22</description>
<categories>
</categories>
</category>
<category>
<name>V3.a</name>
<description>Min. and max. Via3 width = 0.19</description>
<categories>
</categories>
</category>
<category>
<name>V3.b</name>
<description>Min. Via3 space = 0.22</description>
<categories>
</categories>
</category>
<category>
<name>V4.a</name>
<description>Min. and max. Via4 width = 0.19</description>
<categories>
</categories>
</category>
<category>
<name>V4.b</name>
<description>Min. Via4 space = 0.22</description>
<categories>
</categories>
</category>
<category>
<name>TV1.a</name>
<description>Min. and max. TopVia1 width = 0.42</description>
<categories>
</categories>
</category>
<category>
<name>TV1.b</name>
<description>Min. TopVia1 space = 0.42</description>
<categories>
</categories>
</category>
<category>
<name>TM1.a</name>
<description>Min. TopMetal1 width = 1.64</description>
<categories>
</categories>
</category>
<category>
<name>TM1.b</name>
<description>Min. TopMetal1 space or notch = 1.64</description>
<categories>
</categories>
</category>
<category>
<name>TM1.c/d</name>
<description>Global TopMetal1 density [%] = 25.00 .. 70.00</description>
<categories>
</categories>
</category>
<category>
<name>TV2.a</name>
<description>Min. and max. TopVia2 width = 0.90</description>
<categories>
</categories>
</category>
<category>
<name>TV2.b</name>
<description>Min. TopVia2 space = 1.06</description>
<categories>
</categories>
</category>
<category>
<name>TM2.a</name>
<description>Min. TopMetal2 width = 2.00</description>
<categories>
</categories>
</category>
<category>
<name>TM2.b</name>
<description>Min. TopMetal2 space or notch = 2.00</description>
<categories>
</categories>
</category>
<category>
<name>TM2.c/d</name>
<description>Global TopMetal2 density [%] = 25.00 .. 70.00</description>
<categories>
</categories>
</category>
<category>
<name>Pas.a</name>
<description>Min. Passiv width = 2.10</description>
<categories>
</categories>
</category>
<category>
<name>Pas.b</name>
<description>Min. Passiv space or notch = 3.50</description>
<categories>
</categories>
</category>
<category>
<name>Pin.a</name>
<description>Min. Activ enclosure of Activ:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.b</name>
<description>Min. GatPoly enclosure of GatPoly:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.e</name>
<description>Min. Metal1 enclosure of Metal1:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.f.M2</name>
<description>Min. Metal2 enclosure of Metal2:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.f.M3</name>
<description>Min. Metal3 enclosure of Metal3:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.f.M4</name>
<description>Min. Metal4 enclosure of Metal4:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.f.M5</name>
<description>Min. Metal5 enclosure of Metal5:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.g</name>
<description>Min. TopMetal1 enclosure of TopMetal1:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.h</name>
<description>Min. TopMetal2 enclosure of TopMetal2:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.a</name>
<description>Min. LBE width = 100.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.b</name>
<description>Max. LBE width = 1500.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.b1</name>
<description>Max. LBE area (µm²) = 250000.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.c</name>
<description>Min. LBE space or notch = 100.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.d</name>
<description>Min. LBE space to inner edge of EdgeSeal = 150.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.h</name>
<description>No LBE ring allowed</description>
<categories>
</categories>
</category>
<category>
<name>LBE.i</name>
<description>Max. global LBE density [%] = 20.00</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.BiWind</name>
<description>Forbidden drawn layer BiWind on GDS layer 3/0 = 3/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.PEmWind</name>
<description>Forbidden drawn layer PEmWind on GDS layer 11/0 = 11/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.BasPoly</name>
<description>Forbidden drawn layer BasPoly on GDS layer 13/0 = 13/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.DeepCo</name>
<description>Forbidden drawn layer DeepCo on GDS layer 35/0 = 35/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.PEmPoly</name>
<description>Forbidden drawn layer PEmPoly on GDS layer 53/0 = 53/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.EmPoly</name>
<description>Forbidden gen./drawn layer EmPoly on GDS layer 53/0 = 53/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.LDMOS</name>
<description>Forbidden drawn layer LDMOS on GDS layer 57/0 = 57/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.PBiWind</name>
<description>Forbidden drawn layer PBiWind on GDS layer 58/0 = 58/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.Flash</name>
<description>Forbidden drawn layer Flash on GDS layer 71/0 = 71/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.ColWind</name>
<description>Forbidden drawn layer ColWind on GDS layer 139/0 = 139/0</description>
<categories>
</categories>
</category>
</categories>
<cells>
<cell>
<name>full_bandgap</name>
<variant/>
<layout-name/>
<references>
</references>
</cell>
</cells>
<items>
</items>
</report-database>

15532
modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/sg13g2_maximal.lyrdb Normal file
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688
modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/sg13g2_minimal.lyrdb Normal file
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@ -0,0 +1,688 @@
<?xml version="1.0" encoding="utf-8"?>
<report-database>
<description>design rules: sg13g2_minimal | layout cell: two_stage_OTA_layout</description>
<original-file>two_stage_OTA_layout.gds</original-file>
<generator>drc: script='/home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_minimal.lydrc'</generator>
<top-cell>two_stage_OTA_layout</top-cell>
<tags>
</tags>
<categories>
<category>
<name>Act.a</name>
<description>Min. Activ width = 0.15</description>
<categories>
</categories>
</category>
<category>
<name>Act.b</name>
<description>Min. Activ space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>AFil.g/g1</name>
<description>Global Activ density [%] = 35.00 .. 55.00</description>
<categories>
</categories>
</category>
<category>
<name>AFil.g2/g3</name>
<description>Activ coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 65.00</description>
<categories>
</categories>
</category>
<category>
<name>TGO.f</name>
<description>Min. ThickGateOx width = 0.86</description>
<categories>
</categories>
</category>
<category>
<name>Gat.a</name>
<description>Min. GatPoly width = 0.13</description>
<categories>
</categories>
</category>
<category>
<name>Gat.b</name>
<description>Min. GatPoly space or notch = 0.18</description>
<categories>
</categories>
</category>
<category>
<name>Gat.d</name>
<description>Min. GatPoly space to Activ = 0.07</description>
<categories>
</categories>
</category>
<category>
<name>GFil.g</name>
<description>Min. global GatPoly density [%] = 15.00</description>
<categories>
</categories>
</category>
<category>
<name>Cnt.a</name>
<description>Min. and max. Cont width = 0.16</description>
<categories>
</categories>
</category>
<category>
<name>Cnt.b</name>
<description>Min. Cont space = 0.18</description>
<categories>
</categories>
</category>
<category>
<name>M1.a</name>
<description>Min. Metal1 width = 0.16</description>
<categories>
</categories>
</category>
<category>
<name>M1.b</name>
<description>Min. Metal1 space or notch = 0.18</description>
<categories>
</categories>
</category>
<category>
<name>M1.j/k</name>
<description>Global Metal1 density [%] = 35.0 .. 60.0</description>
<categories>
</categories>
</category>
<category>
<name>M2.a</name>
<description>Min. Metal2 width = 0.20</description>
<categories>
</categories>
</category>
<category>
<name>M2.b</name>
<description>Min. Metal2 space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>M2.j/k</name>
<description>Global Metal2 density [%] = 35.00 .. 60.00</description>
<categories>
</categories>
</category>
<category>
<name>M3.a</name>
<description>Min. Metal3 width = 0.20</description>
<categories>
</categories>
</category>
<category>
<name>M3.b</name>
<description>Min. Metal3 space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>M3.j/k</name>
<description>Global Metal3 density [%] = 35.00 .. 60.00</description>
<categories>
</categories>
</category>
<category>
<name>M4.a</name>
<description>Min. Metal4 width = 0.20</description>
<categories>
</categories>
</category>
<category>
<name>M4.b</name>
<description>Min. Metal4 space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>M4.j/k</name>
<description>Global Metal4 density [%] = 35.00 .. 60.00</description>
<categories>
</categories>
</category>
<category>
<name>M5.a</name>
<description>Min. Metal5 width = 0.20</description>
<categories>
</categories>
</category>
<category>
<name>M5.b</name>
<description>Min. Metal5 space or notch = 0.21</description>
<categories>
</categories>
</category>
<category>
<name>M5.j/k</name>
<description>Global Metal5 density [%] = 35.00 .. 60.00</description>
<categories>
</categories>
</category>
<category>
<name>M1Fil.h/k</name>
<description>Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>M2Fil.h/k</name>
<description>Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>M3Fil.h/k</name>
<description>Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>M4Fil.h/k</name>
<description>Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>M5Fil.h/k</name>
<description>Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00 .. 75.00</description>
<categories>
</categories>
</category>
<category>
<name>V1.a</name>
<description>Min. and max. Via1 width = 0.19</description>
<categories>
</categories>
</category>
<category>
<name>V1.b</name>
<description>Min. Via1 space = 0.22</description>
<categories>
</categories>
</category>
<category>
<name>V2.a</name>
<description>Min. and max. Via2 width = 0.19</description>
<categories>
</categories>
</category>
<category>
<name>V2.b</name>
<description>Min. Via2 space = 0.22</description>
<categories>
</categories>
</category>
<category>
<name>V3.a</name>
<description>Min. and max. Via3 width = 0.19</description>
<categories>
</categories>
</category>
<category>
<name>V3.b</name>
<description>Min. Via3 space = 0.22</description>
<categories>
</categories>
</category>
<category>
<name>V4.a</name>
<description>Min. and max. Via4 width = 0.19</description>
<categories>
</categories>
</category>
<category>
<name>V4.b</name>
<description>Min. Via4 space = 0.22</description>
<categories>
</categories>
</category>
<category>
<name>TV1.a</name>
<description>Min. and max. TopVia1 width = 0.42</description>
<categories>
</categories>
</category>
<category>
<name>TV1.b</name>
<description>Min. TopVia1 space = 0.42</description>
<categories>
</categories>
</category>
<category>
<name>TM1.a</name>
<description>Min. TopMetal1 width = 1.64</description>
<categories>
</categories>
</category>
<category>
<name>TM1.b</name>
<description>Min. TopMetal1 space or notch = 1.64</description>
<categories>
</categories>
</category>
<category>
<name>TM1.c/d</name>
<description>Global TopMetal1 density [%] = 25.00 .. 70.00</description>
<categories>
</categories>
</category>
<category>
<name>TV2.a</name>
<description>Min. and max. TopVia2 width = 0.90</description>
<categories>
</categories>
</category>
<category>
<name>TV2.b</name>
<description>Min. TopVia2 space = 1.06</description>
<categories>
</categories>
</category>
<category>
<name>TM2.a</name>
<description>Min. TopMetal2 width = 2.00</description>
<categories>
</categories>
</category>
<category>
<name>TM2.b</name>
<description>Min. TopMetal2 space or notch = 2.00</description>
<categories>
</categories>
</category>
<category>
<name>TM2.c/d</name>
<description>Global TopMetal2 density [%] = 25.00 .. 70.00</description>
<categories>
</categories>
</category>
<category>
<name>Pas.a</name>
<description>Min. Passiv width = 2.10</description>
<categories>
</categories>
</category>
<category>
<name>Pas.b</name>
<description>Min. Passiv space or notch = 3.50</description>
<categories>
</categories>
</category>
<category>
<name>Pin.a</name>
<description>Min. Activ enclosure of Activ:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.b</name>
<description>Min. GatPoly enclosure of GatPoly:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.e</name>
<description>Min. Metal1 enclosure of Metal1:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.f.M2</name>
<description>Min. Metal2 enclosure of Metal2:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.f.M3</name>
<description>Min. Metal3 enclosure of Metal3:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.f.M4</name>
<description>Min. Metal4 enclosure of Metal4:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.f.M5</name>
<description>Min. Metal5 enclosure of Metal5:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.g</name>
<description>Min. TopMetal1 enclosure of TopMetal1:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>Pin.h</name>
<description>Min. TopMetal2 enclosure of TopMetal2:pin = 0.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.a</name>
<description>Min. LBE width = 100.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.b</name>
<description>Max. LBE width = 1500.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.b1</name>
<description>Max. LBE area (µm²) = 250000.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.c</name>
<description>Min. LBE space or notch = 100.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.d</name>
<description>Min. LBE space to inner edge of EdgeSeal = 150.00</description>
<categories>
</categories>
</category>
<category>
<name>LBE.h</name>
<description>No LBE ring allowed</description>
<categories>
</categories>
</category>
<category>
<name>LBE.i</name>
<description>Max. global LBE density [%] = 20.00</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.BiWind</name>
<description>Forbidden drawn layer BiWind on GDS layer 3/0 = 3/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.PEmWind</name>
<description>Forbidden drawn layer PEmWind on GDS layer 11/0 = 11/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.BasPoly</name>
<description>Forbidden drawn layer BasPoly on GDS layer 13/0 = 13/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.DeepCo</name>
<description>Forbidden drawn layer DeepCo on GDS layer 35/0 = 35/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.PEmPoly</name>
<description>Forbidden drawn layer PEmPoly on GDS layer 53/0 = 53/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.EmPoly</name>
<description>Forbidden gen./drawn layer EmPoly on GDS layer 53/0 = 53/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.LDMOS</name>
<description>Forbidden drawn layer LDMOS on GDS layer 57/0 = 57/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.PBiWind</name>
<description>Forbidden drawn layer PBiWind on GDS layer 58/0 = 58/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.Flash</name>
<description>Forbidden drawn layer Flash on GDS layer 71/0 = 71/0</description>
<categories>
</categories>
</category>
<category>
<name>forbidden.ColWind</name>
<description>Forbidden drawn layer ColWind on GDS layer 139/0 = 139/0</description>
<categories>
</categories>
</category>
</categories>
<cells>
<cell>
<name>two_stage_OTA_layout</name>
<variant/>
<layout-name/>
<references>
</references>
</cell>
</cells>
<items>
<item>
<tags/>
<category>'M1.b'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>edge-pair: (59.965,6.005;69.375,6.005)|(69.375,6.13;59.965,6.13)</value>
</values>
</item>
<item>
<tags/>
<category>'M1.b'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>edge-pair: (59.835,6.005;69.505,6.005)|(69.375,6.13;59.965,6.13)</value>
</values>
</item>
<item>
<tags/>
<category>'M1.j/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'M2.b'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>edge-pair: (59.965,6.005;69.375,6.005)|(69.375,6.13;59.965,6.13)</value>
</values>
</item>
<item>
<tags/>
<category>'M2.b'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>edge-pair: (59.796,6.005;69.375,6.005)|(69.375,6.13;59.965,6.13)</value>
</values>
</item>
<item>
<tags/>
<category>'M2.j/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'M3.j/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'M4.j/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'M5.j/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'M1Fil.h/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'M2Fil.h/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'M3Fil.h/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'M4Fil.h/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'M5Fil.h/k'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'TM1.c/d'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'TM2.c/d'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (0.875,-31.715;0.875,7.38;70.515,7.38;70.515,-31.715)</value>
</values>
</item>
<item>
<tags/>
<category>'Pin.f.M2'</category>
<cell>two_stage_OTA_layout</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<comment/>
<image/>
<values>
<value>polygon: (27.925,3.955;27.925,4.285;27.985,4.285;27.985,3.955)</value>
</values>
</item>
</items>
</report-database>

2
modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/two_stage_OTA_layout_extracted.cir
View File

@ -1,4 +1,4 @@
* Extracted by KLayout with SG13G2 LVS runset on : 28/03/2025 08:06
* Extracted by KLayout with SG13G2 LVS runset on : 17/07/2025 11:31
.SUBCKT two_stage_OTA_layout vss vdd dn3 iout vout dn2 v+ v\x2d vss$1 dn4
M$1 vss dn3 dn3 vss sg13_lv_nmos L=9.75u W=0.72u AS=0.2448p AD=0.2448p PS=2.12u

100
modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/comparator_tb.sch
View File

@ -12,7 +12,7 @@ ypos2=2
divy=5
subdivy=1
unity=1
x1=-1e-07
x1=0
divx=5
subdivx=4
@ -24,10 +24,10 @@ dataset=-1
unitx=1
logx=0
logy=0
x2=9e-07
x2=1e-06
color=4
node=clk}
B 2 20 -885 820 -485 {flags=graph
B 2 20 -855 820 -455 {flags=graph
y1=0.59
y2=0.61
ypos1=0
@ -35,7 +35,7 @@ ypos2=2
divy=5
subdivy=1
unity=1
x1=-1e-07
x1=0
divx=5
subdivx=4
@ -47,7 +47,7 @@ dataset=-1
unitx=1
logx=0
logy=0
x2=9e-07
x2=1e-06
color=4
@ -60,7 +60,7 @@ ypos2=2
divy=5
subdivy=1
unity=1
x1=-1e-07
x1=0
divx=5
subdivx=4
@ -72,20 +72,20 @@ dataset=-1
unitx=1
logx=0
logy=0
x2=9e-07
x2=1e-06
color=4
node=vout}
B 2 850 -805 1650 -405 {flags=graph
y1=-0.7005027
y2=1.1959773
y1=1.1
y2=1.2
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=-1e-07
x1=0
divx=5
subdivx=4
@ -97,7 +97,7 @@ dataset=-1
unitx=1
logx=0
logy=0
x2=9e-07
x2=1e-06
color=4
node=outp}
@ -109,7 +109,7 @@ ypos2=2
divy=5
subdivy=1
unity=1
x1=-1e-07
x1=0
divx=5
subdivx=4
@ -121,7 +121,7 @@ dataset=-1
unitx=1
logx=0
logy=0
x2=9e-07
x2=1e-06
color=4
@ -166,8 +166,6 @@ N -610 -80 -570 -80 {
lab=GND}
N -540 -100 -540 -80 {
lab=GND}
N 80 -300 80 -280 {
lab=vinp}
N 60 -280 80 -280 {
lab=vinp}
N 80 -160 80 -140 {
@ -176,37 +174,44 @@ N 60 -160 80 -160 {
lab=vbias}
N 80 -80 80 -60 {
lab=GND}
N 80 -380 80 -360 {
lab=GND}
N 460 -150 460 -140 {
lab=GND}
N 460 -300 460 -290 {
lab=GND}
C {devices/code_shown.sym} -675 -490 0 0 {name=MODEL only_toplevel=false
N 80 -300 80 -280 {
lab=vinp}
N 80 -380 80 -360 {
lab=GND}
C {devices/code_shown.sym} -775 -550 0 0 {name=MODEL only_toplevel=false
format="tcleval( @value )"
value="
.lib cornerMOSlv.lib mos_tt
"}
C {devices/code_shown.sym} -685 -780 0 0 {name=NGSPICE only_toplevel=false
C {devices/code_shown.sym} -865 -1040 0 0 {name=NGSPICE only_toplevel=false
value="
.include comparator_tb.save
.param temp=27
.param clock = 100e6 ; 100 MHz clock
.param period = \{1/clock\}
.param num_cycles = 100
.param tr = \{num_cycles * period\}
.control
save all
* Operating point simulation
op
.param clock = 100e6 ; 100 MHz clock
.param period = 1 / clock
.param num_cycles = 100 ; number of evaluation cycles
.param tr = num_cycles * period
write comparator_tb.raw
set appendwrite
* Transient analysis
tran 500p 1u
.save all
let vindiff = (v(vinp))-(v(vbias))
let vindiff = v(vinp) - v(vbias)
let clk = v(clk)
let vout = (v(outp))-(v(outm))
write output_file.raw
let vout = v(outp) - v(outm)
write comparator_tb.raw
.endc
"}
C {launcher.sym} -160 -855 0 0 {name=h5
descr="load waves"
tclcommand="xschem raw_read $netlist_dir/output_file.raw tran"
}
C {vsource.sym} -610 -130 0 0 {name=V3 value="DC 1.2"}
C {vsource.sym} -540 -130 0 0 {name=V4 value="DC 0.6"}
C {gnd.sym} -310 -70 0 0 {name=l1 lab=GND}
@ -250,3 +255,36 @@ device="ceramic capacitor"}
C {gnd.sym} 460 -140 0 0 {name=l6 lab=GND}
C {gnd.sym} 460 -300 2 0 {name=l7 lab=GND}
C {dynamic_comparator.sym} 270 -220 0 0 {name=x1}
C {sg13g2_pr/annotate_fet_params.sym} -240 -1070 0 0 {name=annot1 ref=M3}
C {devices/launcher.sym} -210 -810 0 0 {name=h1
descr="OP annotate"
tclcommand="xschem annotate_op"
}
C {launcher.sym} -210 -850 0 0 {name=h5
descr="load waves"
tclcommand="xschem raw_read $netlist_dir/comparator_tb.raw tran"
}
C {launcher.sym} -210 -765 0 0 {name=h2
descr=SimulateNGSPICE
tclcommand="
# Setup the default simulation commands if not already set up
# for example by already launched simulations.
set_sim_defaults
puts $sim(spice,1,cmd)
# Change the Xyce command. In the spice category there are currently
# 5 commands (0, 1, 2, 3, 4). Command 3 is the Xyce batch
# you can get the number by querying $sim(spice,n)
set sim(spice,1,cmd) \{ngspice \\"$N\\" -a\}
# change the simulator to be used (Xyce)
set sim(spice,default) 0
# Create FET and BIP .save file
mkdir -p $netlist_dir
write_data [save_params] $netlist_dir/[file rootname [file tail [xschem get current_name]]].save
# run netlist and simulation
xschem netlist
simulate
"}

122
modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/simulations/.save Normal file
View File

@ -0,0 +1,122 @@
* Place this .save file with a .include line in your testbench
.save @n.x1.xm13.nsg13_lv_pmos[ids]
.save @n.x1.xm13.nsg13_lv_pmos[gm]
.save @n.x1.xm13.nsg13_lv_pmos[gds]
.save @n.x1.xm13.nsg13_lv_pmos[vth]
.save @n.x1.xm13.nsg13_lv_pmos[vgs]
.save @n.x1.xm13.nsg13_lv_pmos[vdss]
.save @n.x1.xm13.nsg13_lv_pmos[vds]
.save @n.x1.xm13.nsg13_lv_pmos[cgg]
.save @n.x1.xm13.nsg13_lv_pmos[cgsol]
.save @n.x1.xm13.nsg13_lv_pmos[cgdol]
.save @n.x1.xm3.nsg13_lv_pmos[ids]
.save @n.x1.xm3.nsg13_lv_pmos[gm]
.save @n.x1.xm3.nsg13_lv_pmos[gds]
.save @n.x1.xm3.nsg13_lv_pmos[vth]
.save @n.x1.xm3.nsg13_lv_pmos[vgs]
.save @n.x1.xm3.nsg13_lv_pmos[vdss]
.save @n.x1.xm3.nsg13_lv_pmos[vds]
.save @n.x1.xm3.nsg13_lv_pmos[cgg]
.save @n.x1.xm3.nsg13_lv_pmos[cgsol]
.save @n.x1.xm3.nsg13_lv_pmos[cgdol]
.save @n.x1.xm2.nsg13_lv_pmos[ids]
.save @n.x1.xm2.nsg13_lv_pmos[gm]
.save @n.x1.xm2.nsg13_lv_pmos[gds]
.save @n.x1.xm2.nsg13_lv_pmos[vth]
.save @n.x1.xm2.nsg13_lv_pmos[vgs]
.save @n.x1.xm2.nsg13_lv_pmos[vdss]
.save @n.x1.xm2.nsg13_lv_pmos[vds]
.save @n.x1.xm2.nsg13_lv_pmos[cgg]
.save @n.x1.xm2.nsg13_lv_pmos[cgsol]
.save @n.x1.xm2.nsg13_lv_pmos[cgdol]
.save @n.x1.xm1.nsg13_lv_pmos[ids]
.save @n.x1.xm1.nsg13_lv_pmos[gm]
.save @n.x1.xm1.nsg13_lv_pmos[gds]
.save @n.x1.xm1.nsg13_lv_pmos[vth]
.save @n.x1.xm1.nsg13_lv_pmos[vgs]
.save @n.x1.xm1.nsg13_lv_pmos[vdss]
.save @n.x1.xm1.nsg13_lv_pmos[vds]
.save @n.x1.xm1.nsg13_lv_pmos[cgg]
.save @n.x1.xm1.nsg13_lv_pmos[cgsol]
.save @n.x1.xm1.nsg13_lv_pmos[cgdol]
.save @n.x1.xm4.nsg13_lv_pmos[ids]
.save @n.x1.xm4.nsg13_lv_pmos[gm]
.save @n.x1.xm4.nsg13_lv_pmos[gds]
.save @n.x1.xm4.nsg13_lv_pmos[vth]
.save @n.x1.xm4.nsg13_lv_pmos[vgs]
.save @n.x1.xm4.nsg13_lv_pmos[vdss]
.save @n.x1.xm4.nsg13_lv_pmos[vds]
.save @n.x1.xm4.nsg13_lv_pmos[cgg]
.save @n.x1.xm4.nsg13_lv_pmos[cgsol]
.save @n.x1.xm4.nsg13_lv_pmos[cgdol]
.save @n.x1.xm5.nsg13_lv_pmos[ids]
.save @n.x1.xm5.nsg13_lv_pmos[gm]
.save @n.x1.xm5.nsg13_lv_pmos[gds]
.save @n.x1.xm5.nsg13_lv_pmos[vth]
.save @n.x1.xm5.nsg13_lv_pmos[vgs]
.save @n.x1.xm5.nsg13_lv_pmos[vdss]
.save @n.x1.xm5.nsg13_lv_pmos[vds]
.save @n.x1.xm5.nsg13_lv_pmos[cgg]
.save @n.x1.xm5.nsg13_lv_pmos[cgsol]
.save @n.x1.xm5.nsg13_lv_pmos[cgdol]
.save @n.x1.xm11.nsg13_lv_nmos[ids]
.save @n.x1.xm11.nsg13_lv_nmos[gm]
.save @n.x1.xm11.nsg13_lv_nmos[gds]
.save @n.x1.xm11.nsg13_lv_nmos[vth]
.save @n.x1.xm11.nsg13_lv_nmos[vgs]
.save @n.x1.xm11.nsg13_lv_nmos[vdss]
.save @n.x1.xm11.nsg13_lv_nmos[vds]
.save @n.x1.xm11.nsg13_lv_nmos[cgg]
.save @n.x1.xm11.nsg13_lv_nmos[cgsol]
.save @n.x1.xm11.nsg13_lv_nmos[cgdol]
.save @n.x1.xm12.nsg13_lv_nmos[ids]
.save @n.x1.xm12.nsg13_lv_nmos[gm]
.save @n.x1.xm12.nsg13_lv_nmos[gds]
.save @n.x1.xm12.nsg13_lv_nmos[vth]
.save @n.x1.xm12.nsg13_lv_nmos[vgs]
.save @n.x1.xm12.nsg13_lv_nmos[vdss]
.save @n.x1.xm12.nsg13_lv_nmos[vds]
.save @n.x1.xm12.nsg13_lv_nmos[cgg]
.save @n.x1.xm12.nsg13_lv_nmos[cgsol]
.save @n.x1.xm12.nsg13_lv_nmos[cgdol]
.save @n.x1.xm6.nsg13_lv_nmos[ids]
.save @n.x1.xm6.nsg13_lv_nmos[gm]
.save @n.x1.xm6.nsg13_lv_nmos[gds]
.save @n.x1.xm6.nsg13_lv_nmos[vth]
.save @n.x1.xm6.nsg13_lv_nmos[vgs]
.save @n.x1.xm6.nsg13_lv_nmos[vdss]
.save @n.x1.xm6.nsg13_lv_nmos[vds]
.save @n.x1.xm6.nsg13_lv_nmos[cgg]
.save @n.x1.xm6.nsg13_lv_nmos[cgsol]
.save @n.x1.xm6.nsg13_lv_nmos[cgdol]
.save @n.x1.xm10.nsg13_lv_nmos[ids]
.save @n.x1.xm10.nsg13_lv_nmos[gm]
.save @n.x1.xm10.nsg13_lv_nmos[gds]
.save @n.x1.xm10.nsg13_lv_nmos[vth]
.save @n.x1.xm10.nsg13_lv_nmos[vgs]
.save @n.x1.xm10.nsg13_lv_nmos[vdss]
.save @n.x1.xm10.nsg13_lv_nmos[vds]
.save @n.x1.xm10.nsg13_lv_nmos[cgg]
.save @n.x1.xm10.nsg13_lv_nmos[cgsol]
.save @n.x1.xm10.nsg13_lv_nmos[cgdol]
.save @n.x1.xm7.nsg13_lv_nmos[ids]
.save @n.x1.xm7.nsg13_lv_nmos[gm]
.save @n.x1.xm7.nsg13_lv_nmos[gds]
.save @n.x1.xm7.nsg13_lv_nmos[vth]
.save @n.x1.xm7.nsg13_lv_nmos[vgs]
.save @n.x1.xm7.nsg13_lv_nmos[vdss]
.save @n.x1.xm7.nsg13_lv_nmos[vds]
.save @n.x1.xm7.nsg13_lv_nmos[cgg]
.save @n.x1.xm7.nsg13_lv_nmos[cgsol]
.save @n.x1.xm7.nsg13_lv_nmos[cgdol]
.save @n.x1.xm8.nsg13_lv_nmos[ids]
.save @n.x1.xm8.nsg13_lv_nmos[gm]
.save @n.x1.xm8.nsg13_lv_nmos[gds]
.save @n.x1.xm8.nsg13_lv_nmos[vth]
.save @n.x1.xm8.nsg13_lv_nmos[vgs]
.save @n.x1.xm8.nsg13_lv_nmos[vdss]
.save @n.x1.xm8.nsg13_lv_nmos[vds]
.save @n.x1.xm8.nsg13_lv_nmos[cgg]
.save @n.x1.xm8.nsg13_lv_nmos[cgsol]
.save @n.x1.xm8.nsg13_lv_nmos[cgdol]

122
modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/simulations/comparator_tb.save Normal file
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@ -0,0 +1,122 @@
* Place this .save file with a .include line in your testbench
.save @n.x1.xm13.nsg13_lv_pmos[ids]
.save @n.x1.xm13.nsg13_lv_pmos[gm]
.save @n.x1.xm13.nsg13_lv_pmos[gds]
.save @n.x1.xm13.nsg13_lv_pmos[vth]
.save @n.x1.xm13.nsg13_lv_pmos[vgs]
.save @n.x1.xm13.nsg13_lv_pmos[vdss]
.save @n.x1.xm13.nsg13_lv_pmos[vds]
.save @n.x1.xm13.nsg13_lv_pmos[cgg]
.save @n.x1.xm13.nsg13_lv_pmos[cgsol]
.save @n.x1.xm13.nsg13_lv_pmos[cgdol]
.save @n.x1.xm3.nsg13_lv_pmos[ids]
.save @n.x1.xm3.nsg13_lv_pmos[gm]
.save @n.x1.xm3.nsg13_lv_pmos[gds]
.save @n.x1.xm3.nsg13_lv_pmos[vth]
.save @n.x1.xm3.nsg13_lv_pmos[vgs]
.save @n.x1.xm3.nsg13_lv_pmos[vdss]
.save @n.x1.xm3.nsg13_lv_pmos[vds]
.save @n.x1.xm3.nsg13_lv_pmos[cgg]
.save @n.x1.xm3.nsg13_lv_pmos[cgsol]
.save @n.x1.xm3.nsg13_lv_pmos[cgdol]
.save @n.x1.xm2.nsg13_lv_pmos[ids]
.save @n.x1.xm2.nsg13_lv_pmos[gm]
.save @n.x1.xm2.nsg13_lv_pmos[gds]
.save @n.x1.xm2.nsg13_lv_pmos[vth]
.save @n.x1.xm2.nsg13_lv_pmos[vgs]
.save @n.x1.xm2.nsg13_lv_pmos[vdss]
.save @n.x1.xm2.nsg13_lv_pmos[vds]
.save @n.x1.xm2.nsg13_lv_pmos[cgg]
.save @n.x1.xm2.nsg13_lv_pmos[cgsol]
.save @n.x1.xm2.nsg13_lv_pmos[cgdol]
.save @n.x1.xm1.nsg13_lv_pmos[ids]
.save @n.x1.xm1.nsg13_lv_pmos[gm]
.save @n.x1.xm1.nsg13_lv_pmos[gds]
.save @n.x1.xm1.nsg13_lv_pmos[vth]
.save @n.x1.xm1.nsg13_lv_pmos[vgs]
.save @n.x1.xm1.nsg13_lv_pmos[vdss]
.save @n.x1.xm1.nsg13_lv_pmos[vds]
.save @n.x1.xm1.nsg13_lv_pmos[cgg]
.save @n.x1.xm1.nsg13_lv_pmos[cgsol]
.save @n.x1.xm1.nsg13_lv_pmos[cgdol]
.save @n.x1.xm4.nsg13_lv_pmos[ids]
.save @n.x1.xm4.nsg13_lv_pmos[gm]
.save @n.x1.xm4.nsg13_lv_pmos[gds]
.save @n.x1.xm4.nsg13_lv_pmos[vth]
.save @n.x1.xm4.nsg13_lv_pmos[vgs]
.save @n.x1.xm4.nsg13_lv_pmos[vdss]
.save @n.x1.xm4.nsg13_lv_pmos[vds]
.save @n.x1.xm4.nsg13_lv_pmos[cgg]
.save @n.x1.xm4.nsg13_lv_pmos[cgsol]
.save @n.x1.xm4.nsg13_lv_pmos[cgdol]
.save @n.x1.xm5.nsg13_lv_pmos[ids]
.save @n.x1.xm5.nsg13_lv_pmos[gm]
.save @n.x1.xm5.nsg13_lv_pmos[gds]
.save @n.x1.xm5.nsg13_lv_pmos[vth]
.save @n.x1.xm5.nsg13_lv_pmos[vgs]
.save @n.x1.xm5.nsg13_lv_pmos[vdss]
.save @n.x1.xm5.nsg13_lv_pmos[vds]
.save @n.x1.xm5.nsg13_lv_pmos[cgg]
.save @n.x1.xm5.nsg13_lv_pmos[cgsol]
.save @n.x1.xm5.nsg13_lv_pmos[cgdol]
.save @n.x1.xm11.nsg13_lv_nmos[ids]
.save @n.x1.xm11.nsg13_lv_nmos[gm]
.save @n.x1.xm11.nsg13_lv_nmos[gds]
.save @n.x1.xm11.nsg13_lv_nmos[vth]
.save @n.x1.xm11.nsg13_lv_nmos[vgs]
.save @n.x1.xm11.nsg13_lv_nmos[vdss]
.save @n.x1.xm11.nsg13_lv_nmos[vds]
.save @n.x1.xm11.nsg13_lv_nmos[cgg]
.save @n.x1.xm11.nsg13_lv_nmos[cgsol]
.save @n.x1.xm11.nsg13_lv_nmos[cgdol]
.save @n.x1.xm12.nsg13_lv_nmos[ids]
.save @n.x1.xm12.nsg13_lv_nmos[gm]
.save @n.x1.xm12.nsg13_lv_nmos[gds]
.save @n.x1.xm12.nsg13_lv_nmos[vth]
.save @n.x1.xm12.nsg13_lv_nmos[vgs]
.save @n.x1.xm12.nsg13_lv_nmos[vdss]
.save @n.x1.xm12.nsg13_lv_nmos[vds]
.save @n.x1.xm12.nsg13_lv_nmos[cgg]
.save @n.x1.xm12.nsg13_lv_nmos[cgsol]
.save @n.x1.xm12.nsg13_lv_nmos[cgdol]
.save @n.x1.xm6.nsg13_lv_nmos[ids]
.save @n.x1.xm6.nsg13_lv_nmos[gm]
.save @n.x1.xm6.nsg13_lv_nmos[gds]
.save @n.x1.xm6.nsg13_lv_nmos[vth]
.save @n.x1.xm6.nsg13_lv_nmos[vgs]
.save @n.x1.xm6.nsg13_lv_nmos[vdss]
.save @n.x1.xm6.nsg13_lv_nmos[vds]
.save @n.x1.xm6.nsg13_lv_nmos[cgg]
.save @n.x1.xm6.nsg13_lv_nmos[cgsol]
.save @n.x1.xm6.nsg13_lv_nmos[cgdol]
.save @n.x1.xm10.nsg13_lv_nmos[ids]
.save @n.x1.xm10.nsg13_lv_nmos[gm]
.save @n.x1.xm10.nsg13_lv_nmos[gds]
.save @n.x1.xm10.nsg13_lv_nmos[vth]
.save @n.x1.xm10.nsg13_lv_nmos[vgs]
.save @n.x1.xm10.nsg13_lv_nmos[vdss]
.save @n.x1.xm10.nsg13_lv_nmos[vds]
.save @n.x1.xm10.nsg13_lv_nmos[cgg]
.save @n.x1.xm10.nsg13_lv_nmos[cgsol]
.save @n.x1.xm10.nsg13_lv_nmos[cgdol]
.save @n.x1.xm7.nsg13_lv_nmos[ids]
.save @n.x1.xm7.nsg13_lv_nmos[gm]
.save @n.x1.xm7.nsg13_lv_nmos[gds]
.save @n.x1.xm7.nsg13_lv_nmos[vth]
.save @n.x1.xm7.nsg13_lv_nmos[vgs]
.save @n.x1.xm7.nsg13_lv_nmos[vdss]
.save @n.x1.xm7.nsg13_lv_nmos[vds]
.save @n.x1.xm7.nsg13_lv_nmos[cgg]
.save @n.x1.xm7.nsg13_lv_nmos[cgsol]
.save @n.x1.xm7.nsg13_lv_nmos[cgdol]
.save @n.x1.xm8.nsg13_lv_nmos[ids]
.save @n.x1.xm8.nsg13_lv_nmos[gm]
.save @n.x1.xm8.nsg13_lv_nmos[gds]
.save @n.x1.xm8.nsg13_lv_nmos[vth]
.save @n.x1.xm8.nsg13_lv_nmos[vgs]
.save @n.x1.xm8.nsg13_lv_nmos[vdss]
.save @n.x1.xm8.nsg13_lv_nmos[vds]
.save @n.x1.xm8.nsg13_lv_nmos[cgg]
.save @n.x1.xm8.nsg13_lv_nmos[cgsol]
.save @n.x1.xm8.nsg13_lv_nmos[cgdol]

12
modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/simulations/dc_lv_nmos.save Normal file
View File

@ -0,0 +1,12 @@
* Place this .save file with a .include line in your testbench
.save @n.xm1.nsg13_lv_nmos[ids]
.save @n.xm1.nsg13_lv_nmos[gm]
.save @n.xm1.nsg13_lv_nmos[gds]
.save @n.xm1.nsg13_lv_nmos[vth]
.save @n.xm1.nsg13_lv_nmos[vgs]
.save @n.xm1.nsg13_lv_nmos[vdss]
.save @n.xm1.nsg13_lv_nmos[vds]
.save @n.xm1.nsg13_lv_nmos[cgg]
.save @n.xm1.nsg13_lv_nmos[cgsol]
.save @n.xm1.nsg13_lv_nmos[cgdol]

32
modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/simulations/inv_mc_tb.save Normal file
View File

@ -0,0 +1,32 @@
* Place this .save file with a .include line in your testbench
.save @n.xm1.nsg13_lv_nmos[ids]
.save @n.xm1.nsg13_lv_nmos[gm]
.save @n.xm1.nsg13_lv_nmos[gds]
.save @n.xm1.nsg13_lv_nmos[vth]
.save @n.xm1.nsg13_lv_nmos[vgs]
.save @n.xm1.nsg13_lv_nmos[vdss]
.save @n.xm1.nsg13_lv_nmos[vds]
.save @n.xm1.nsg13_lv_nmos[cgg]
.save @n.xm1.nsg13_lv_nmos[cgsol]
.save @n.xm1.nsg13_lv_nmos[cgdol]
.save @n.xm2.nsg13_lv_pmos[ids]
.save @n.xm2.nsg13_lv_pmos[gm]
.save @n.xm2.nsg13_lv_pmos[gds]
.save @n.xm2.nsg13_lv_pmos[vth]
.save @n.xm2.nsg13_lv_pmos[vgs]
.save @n.xm2.nsg13_lv_pmos[vdss]
.save @n.xm2.nsg13_lv_pmos[vds]
.save @n.xm2.nsg13_lv_pmos[cgg]
.save @n.xm2.nsg13_lv_pmos[cgsol]
.save @n.xm2.nsg13_lv_pmos[cgdol]
.save @n.xm3.nsg13_lv_nmos[ids]
.save @n.xm3.nsg13_lv_nmos[gm]
.save @n.xm3.nsg13_lv_nmos[gds]
.save @n.xm3.nsg13_lv_nmos[vth]
.save @n.xm3.nsg13_lv_nmos[vgs]
.save @n.xm3.nsg13_lv_nmos[vdss]
.save @n.xm3.nsg13_lv_nmos[vds]
.save @n.xm3.nsg13_lv_nmos[cgg]
.save @n.xm3.nsg13_lv_nmos[cgsol]
.save @n.xm3.nsg13_lv_nmos[cgdol]

BIN
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/input_pair_cm.gds
View File

Binary file not shown.

0
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/input_pair_cm.nodes
View File

0
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/input_pair_cm.sim
View File

20
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/output/input_pair_cm__input_pair_cm/magic_CC/input_pair_cm_MAGIC_CC_Script.tcl
View File

@ -1,20 +0,0 @@
# Generated by kpex 0.2.7
crashbackups stop
drc off
gds read /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/input_pair_cm.gds
load input_pair_cm
select top cell
flatten input_pair_cm_flat
load input_pair_cm_flat
cellname delete input_pair_cm -noprompt
cellname rename input_pair_cm_flat input_pair_cm
select top cell
extract path /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/output/input_pair_cm__input_pair_cm/magic_CC
extract all
ext2spice short none
ext2spice merge none
ext2spice cthresh 0.01
ext2spice subcircuits top on
ext2spice format ngspice
ext2spice -p /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/output/input_pair_cm__input_pair_cm/magic_CC -o /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/output/input_pair_cm__input_pair_cm/magic_CC/input_pair_cm.pex.spice
quit -noprompt

72
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/pex_output/input_pair_cm__input_pair_cm/magic_RC/input_pair_cm.ext
View File

@ -1,72 +0,0 @@
timestamp 0
version 8.3
tech ihp-sg13g2
style ngspice()
scale 1000 1 0.5
resistclasses 3000000 67000 110 88 88 88 88 18 11
parameters sg13_lv_pmos l=l w=w a1=as p1=ps a2=ad p2=pd
port "Drain2" 4 2947 3110 2985 3148 m4
port "Drain1" 3 2651 3110 2689 3148 m2
port "vdd" 1 1014 2943 1071 2995 m1
node "a_2357_3299#" 14 387.74 2357 3299 pdif 0 0 0 0 116960 6864 225960 4628 266560 4088 0 0 0 0 0 0 0 0
node "Drain2" 16 550.628 2947 3110 m4 0 0 0 0 116960 6864 32480 1584 500500 7710 245560 3788 0 0 0 0 0 0
node "a_1135_3368#" 11 3257.89 1135 3368 p 0 0 0 0 238002 7698 56404 2350 137250 3702 0 0 0 0 0 0 0 0
node "Drain1" 15 400.094 2651 3110 m2 0 0 0 0 116960 6864 278040 5372 500640 7712 0 0 0 0 0 0 0 0
node "a_1135_3839#" 11 3274.81 1135 3839 p 0 0 0 0 218514 7032 96568 3908 137250 3702 0 0 0 0 0 0 0 0
node "a_1245_3300#" 29 654.46 1245 3300 pdif 0 0 0 0 233920 13728 64960 3168 532840 8172 193480 3044 0 0 0 0 0 0
node "a_1245_3771#" 14 176.751 1245 3771 pdif 0 0 0 0 116960 6864 32480 1584 266560 4088 0 0 0 0 0 0 0 0
node "w_805_2869#" 1513432 0 805 2869 pw 223356 21272 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "vdd" 21 1653.88 1014 2943 m1 0 0 0 0 515840 19840 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUB" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cap "w_805_2869#" "a_1245_3300#" 5.4313
cap "Drain2" "a_2357_3299#" 113.693
cap "w_805_2869#" "vdd" 89.3833
cap "a_2357_3299#" "a_1245_3300#" 1001.64
cap "a_1135_3368#" "w_805_2869#" 7.96269
cap "a_1135_3839#" "Drain1" 775.115
cap "a_2357_3299#" "vdd" 683.256
cap "a_1135_3368#" "a_2357_3299#" 174.98
cap "Drain2" "a_1135_3839#" 427.559
cap "Drain2" "Drain1" 672.32
cap "a_1245_3300#" "a_1135_3839#" 170.175
cap "a_1245_3300#" "Drain1" 3329.35
cap "a_1135_3839#" "vdd" 2780.38
cap "Drain1" "vdd" 523.06
cap "w_805_2869#" "a_1245_3771#" 0.81511
cap "a_1135_3368#" "a_1135_3839#" 1458.76
cap "a_1135_3368#" "Drain1" 86.5205
cap "Drain2" "a_1245_3300#" 6266.07
cap "a_1245_3771#" "a_2357_3299#" 442.031
cap "Drain2" "vdd" 291.445
cap "a_1245_3300#" "vdd" 777.462
cap "a_1135_3368#" "Drain2" 1071.91
cap "w_805_2869#" "a_2357_3299#" 6.30488
cap "a_1135_3368#" "a_1245_3300#" 438.305
cap "a_1135_3368#" "vdd" 2791.94
cap "a_1245_3771#" "a_1135_3839#" 343.444
cap "a_1245_3771#" "Drain1" 2963.26
cap "Drain2" "a_1245_3771#" 96.2132
cap "w_805_2869#" "a_1135_3839#" 8.25481
cap "w_805_2869#" "Drain1" 8.32062
cap "a_1245_3771#" "a_1245_3300#" 646.375
cap "a_2357_3299#" "a_1135_3839#" 380.673
cap "a_2357_3299#" "Drain1" 3505.97
cap "a_1245_3771#" "vdd" 372.673
cap "w_805_2869#" "Drain2" 6.1761
cap "a_1135_3368#" "a_1245_3771#" 107.634
device msubckt sg13_lv_pmos 2357 3367 2358 3368 l=40 w=800 "vdd" "a_1135_3839#" 80 0 "a_2357_3299#" 800 54400,1736 "Drain1" 800 30400,876
device msubckt sg13_lv_pmos 2357 3483 2358 3484 l=40 w=800 "vdd" "a_1135_3839#" 80 0 "Drain1" 800 30400,876 "a_2357_3299#" 800 54400,1736
device msubckt sg13_lv_pmos 1245 3368 1246 3369 l=40 w=800 "vdd" "a_1135_3368#" 80 0 "a_1245_3300#" 800 54400,1736 "Drain2" 800 30400,876
device msubckt sg13_lv_pmos 1245 3484 1246 3485 l=40 w=800 "vdd" "a_1135_3368#" 80 0 "Drain2" 800 30400,876 "a_1245_3300#" 800 54400,1736
device msubckt sg13_lv_pmos 2357 3838 2358 3839 l=40 w=800 "vdd" "a_1135_3368#" 80 0 "a_1245_3300#" 800 54400,1736 "Drain2" 800 30400,876
device msubckt sg13_lv_pmos 2357 3954 2358 3955 l=40 w=800 "vdd" "a_1135_3368#" 80 0 "Drain2" 800 30400,876 "a_1245_3300#" 800 54400,1736
device msubckt sg13_lv_pmos 1245 3839 1246 3840 l=40 w=800 "vdd" "a_1135_3839#" 80 0 "a_1245_3771#" 800 54400,1736 "Drain1" 800 30400,876
device msubckt sg13_lv_pmos 1245 3955 1246 3956 l=40 w=800 "vdd" "a_1135_3839#" 80 0 "Drain1" 800 30400,876 "a_1245_3771#" 800 54400,1736
device msubckt sg13_lv_pmos 2357 4309 2358 4310 l=40 w=800 "vdd" "a_1135_3839#" 80 0 "a_2357_3299#" 800 54400,1736 "Drain1" 800 30400,876
device msubckt sg13_lv_pmos 2357 4425 2358 4426 l=40 w=800 "vdd" "a_1135_3839#" 80 0 "Drain1" 800 30400,876 "a_2357_3299#" 800 54400,1736
device msubckt sg13_lv_pmos 1245 4310 1246 4311 l=40 w=800 "vdd" "a_1135_3368#" 80 0 "a_1245_3300#" 800 54400,1736 "Drain2" 800 30400,876
device msubckt sg13_lv_pmos 1245 4426 1246 4427 l=40 w=800 "vdd" "a_1135_3368#" 80 0 "Drain2" 800 30400,876 "a_1245_3300#" 800 54400,1736
device msubckt sg13_lv_pmos 2357 4780 2358 4781 l=40 w=800 "vdd" "a_1135_3368#" 80 0 "a_1245_3300#" 800 54400,1736 "Drain2" 800 30400,876
device msubckt sg13_lv_pmos 2357 4896 2358 4897 l=40 w=800 "vdd" "a_1135_3368#" 80 0 "Drain2" 800 30400,876 "a_1245_3300#" 800 54400,1736
device msubckt sg13_lv_pmos 1245 4781 1246 4782 l=40 w=800 "vdd" "a_1135_3839#" 80 0 "a_1245_3771#" 800 54400,1736 "Drain1" 800 30400,876
device msubckt sg13_lv_pmos 1245 4897 1246 4898 l=40 w=800 "vdd" "a_1135_3839#" 80 0 "Drain1" 800 30400,876 "a_1245_3771#" 800 54400,1736

4
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/pex_output/input_pair_cm__input_pair_cm/magic_RC/input_pair_cm.res.ext
View File

@ -1,4 +0,0 @@
scale 1000 1 0.5
rnode "Drain2" 0 0 2947 3110 0
rnode "Drain1" 0 0 2651 3110 0
rnode "vdd" 0 0 1014 2943 0

27
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/pex_output/input_pair_cm__input_pair_cm/magic_RC/input_pair_cm_MAGIC_RC_Script.tcl
View File

@ -1,27 +0,0 @@
# Generated by kpex 0.2.7
crashbackups stop
drc off
gds read /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/input_pair_cm.gds
load input_pair_cm
select top cell
flatten input_pair_cm_flat
load input_pair_cm_flat
cellname delete input_pair_cm -noprompt
cellname rename input_pair_cm_flat input_pair_cm
select top cell
extract path /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/pex_output/input_pair_cm__input_pair_cm/magic_RC
extract do resistance
extract all
ext2sim labels on
ext2sim
extresist tolerance 1
extresist all
ext2spice short resistor
ext2spice merge conservative
ext2spice cthresh 0.02
ext2spice rthresh 50
ext2spice extresist on
ext2spice subcircuits top on
ext2spice format ngspice
ext2spice -p /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/pex_output/input_pair_cm__input_pair_cm/magic_RC -o /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/pex_output/input_pair_cm__input_pair_cm/magic_RC/input_pair_cm.pex.spice
quit -noprompt

BIN
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/pex_output/input_pair_cm__input_pair_cm/magic_RC/input_pair_cm_MAGIC_report.rdb.gz
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19
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/run_kpex.sh
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@ -1,19 +0,0 @@
#!/bin/bash
source /home/pedersen/misc/klayout_pex/bin/activate
export KPEX_MAGIC_EXE="$HOME/.local/bin/magic"
echo "KPEX_MAGIC_EXE is: $KPEX_MAGIC_EXE"
kpex \
--pdk ihp_sg13g2 \
--magic \
--gds input_pair_cm.gds \
--schematic schematic_mod/simulations/input_pair_cm.spice \
--cell input_pair_cm \
--magicrc /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/magic/ihp-sg13g2.magicrc\
--magic_mode RC \
--magic_cthresh 0.02 \
--magic_rthresh 50 \
--magic_short resistor \
--magic_merge conservative \
--out_dir ./pex_output

58
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/schematic_mod/input_pair_cm.sch
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@ -1,58 +0,0 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 490 -650 490 -600 {
lab=#net1}
N 810 -650 810 -600 {
lab=#net1}
N 810 -540 810 -470 {
lab=Drain2}
N 650 -650 810 -650 {
lab=#net1}
N 650 -710 650 -650 {
lab=#net1}
N 490 -650 650 -650 {
lab=#net1}
N 650 -570 810 -570 {
lab=#net2}
N 490 -540 490 -470 {
lab=Drain1}
N 440 -570 450 -570 {
lab=v+}
N 850 -570 860 -570 {
lab=v-}
N 650 -570 650 -550 {lab=#net2}
N 490 -570 650 -570 {
lab=#net2}
N 650 -490 650 -470 {lab=#net3}
C {ipin.sym} 440 -570 0 0 {name=p3 lab=v+}
C {ipin.sym} 860 -570 0 1 {name=p4 lab=v-}
C {sg13g2_pr/sg13_lv_pmos.sym} 470 -570 0 0 {name=M2
l=200n
w=32u
ng=4
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 830 -570 0 1 {name=M1
l=200n
w=32u
ng=4
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/ntap1.sym} 650 -520 0 0 {name=R1
model=ntap1
spiceprefix=X
w=0.78e-6
l=0.78e-6
}
C {iopin.sym} 810 -470 0 0 {name=p7 lab=Drain2}
C {iopin.sym} 490 -470 0 0 {name=p1 lab=Drain1}
C {iopin.sym} 650 -470 0 0 {name=p2 lab=vdd}
C {iopin.sym} 650 -710 0 0 {name=p5 lab=top}

58
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/xschem/input_pair_cm.sch
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@ -1,58 +0,0 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 490 -650 490 -600 {
lab=#net1}
N 810 -650 810 -600 {
lab=#net1}
N 810 -540 810 -470 {
lab=Drain2}
N 650 -650 810 -650 {
lab=#net1}
N 650 -710 650 -650 {
lab=#net1}
N 490 -650 650 -650 {
lab=#net1}
N 650 -570 810 -570 {
lab=#net2}
N 490 -540 490 -470 {
lab=Drain1}
N 440 -570 450 -570 {
lab=v+}
N 850 -570 860 -570 {
lab=v-}
N 650 -570 650 -550 {lab=#net2}
N 490 -570 650 -570 {
lab=#net2}
N 650 -490 650 -470 {lab=#net3}
C {ipin.sym} 440 -570 0 0 {name=p3 lab=v+}
C {ipin.sym} 860 -570 0 1 {name=p4 lab=v-}
C {sg13g2_pr/sg13_lv_pmos.sym} 470 -570 0 0 {name=M2
l=200n
w=32u
ng=4
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 830 -570 0 1 {name=M1
l=200n
w=32u
ng=4
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/ntap1.sym} 650 -520 0 0 {name=R1
model=ntap1
spiceprefix=X
w=0.78e-6
l=0.78e-6
}
C {iopin.sym} 810 -470 0 0 {name=p7 lab=Drain2}
C {iopin.sym} 490 -470 0 0 {name=p1 lab=Drain1}
C {iopin.sym} 650 -470 0 0 {name=p2 lab=vdd}
C {iopin.sym} 650 -710 0 0 {name=p5 lab=top}

26
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/input_pair/xschem/input_pair_cm.sym
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@ -1,26 +0,0 @@
v {xschem version=3.4.6 file_version=1.2}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
T {@symname} -76.5 -6 0 0 0.3 0.3 {}
T {@name} 135 -52 0 0 0.2 0.2 {}
P 4 5 130 -40 -130 -40 -130 40 130 40 130 -40 {}
B 5 147.5 -32.5 152.5 -27.5 {name=top dir=inout}
L 7 130 -30 150 -30 {}
T {top} 125 -34 0 1 0.2 0.2 {}
B 5 -152.5 -32.5 -147.5 -27.5 {name=v+ dir=in}
L 4 -150 -30 -130 -30 {}
T {v+} -125 -34 0 0 0.2 0.2 {}
B 5 -152.5 -12.5 -147.5 -7.5 {name=v- dir=in}
L 4 -150 -10 -130 -10 {}
T {v-} -125 -14 0 0 0.2 0.2 {}
B 5 147.5 -12.5 152.5 -7.5 {name=vdd dir=inout}
L 7 130 -10 150 -10 {}
T {vdd} 125 -14 0 1 0.2 0.2 {}
B 5 147.5 7.5 152.5 12.5 {name=Drain1 dir=inout}
L 7 130 10 150 10 {}
T {Drain1} 125 6 0 1 0.2 0.2 {}
B 5 147.5 27.5 152.5 32.5 {name=Drain2 dir=inout}
L 7 130 30 150 30 {}
T {Drain2} 125 26 0 1 0.2 0.2 {}

BIN
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/misc/cross_con.gds
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BIN
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/layout/misc/cross_con_new.gds
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BIN
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/macros/gallery.gds
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251
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/comparator/schematic/dynamic_comparator.sch
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@ -1,251 +0,0 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 490 -650 490 -600 {
lab=#net1}
N 810 -650 810 -600 {
lab=#net1}
N 550 -830 610 -830 {
lab=vbias}
N 650 -930 1060 -930 {
lab=vdd}
N 650 -800 650 -770 {
lab=#net2}
N 1060 -470 1060 -450 {
lab=out-}
N 980 -530 1020 -530 {
lab=#net3}
N 980 -470 980 -420 {
lab=#net3}
N 980 -420 1020 -420 {
lab=#net3}
N 1060 -930 1060 -530 {
lab=vdd}
N 810 -540 810 -470 {
lab=#net3}
N 810 -470 980 -470 {
lab=#net3}
N 980 -530 980 -470 {
lab=#net3}
N 720 -270 720 -230 {
lab=#net3}
N 810 -270 900 -270 {
lab=#net3}
N 900 -270 900 -230 {
lab=#net3}
N 810 -470 810 -270 {
lab=#net3}
N 720 -270 810 -270 {
lab=#net3}
N 810 -130 900 -130 {
lab=gnd}
N 900 -170 900 -130 {
lab=gnd}
N 720 -170 720 -130 {
lab=gnd}
N 810 -200 900 -200 {
lab=gnd}
N 400 -270 400 -230 {
lab=#net4}
N 490 -270 580 -270 {
lab=#net4}
N 580 -270 580 -230 {
lab=#net4}
N 400 -270 490 -270 {
lab=#net4}
N 490 -130 580 -130 {
lab=gnd}
N 580 -170 580 -130 {
lab=gnd}
N 400 -170 400 -130 {
lab=gnd}
N 490 -200 580 -200 {
lab=gnd}
N 650 -650 810 -650 {
lab=#net1}
N 650 -710 650 -650 {
lab=#net1}
N 490 -650 650 -650 {
lab=#net1}
N 650 -930 650 -830 {
lab=vdd}
N 650 -740 700 -740 {
lab=vdd}
N 490 -570 810 -570 {
lab=vdd}
N 320 -470 490 -470 {
lab=#net4}
N 490 -470 490 -270 {
lab=#net4}
N 490 -540 490 -470 {
lab=#net4}
N 240 -470 240 -450 {
lab=out+}
N 280 -530 320 -530 {
lab=#net4}
N 320 -470 320 -420 {
lab=#net4}
N 280 -420 320 -420 {
lab=#net4}
N 320 -530 320 -470 {
lab=#net4}
N 240 -930 240 -530 {
lab=vdd}
N 240 -930 650 -930 {
lab=vdd}
N 240 -130 400 -130 {
lab=gnd}
N 580 -130 720 -130 {
lab=gnd}
N 900 -130 1060 -130 {
lab=gnd}
N 490 -470 680 -200 {
lab=#net4}
N 620 -200 810 -470 {
lab=#net3}
N 140 -470 240 -470 {
lab=out+}
N 240 -500 240 -470 {
lab=out+}
N 1060 -470 1160 -470 {
lab=out-}
N 1060 -500 1060 -470 {
lab=out-}
N 330 -200 360 -200 {
lab=clk}
N 440 -570 450 -570 {
lab=v+}
N 850 -570 860 -570 {
lab=v-}
N 360 -740 610 -740 {
lab=clk}
N 360 -740 360 -200 {
lab=clk}
N 1060 -420 1060 -130 {
lab=gnd}
N 810 -200 810 -130 {
lab=gnd}
N 720 -200 810 -200 {
lab=gnd}
N 720 -130 810 -130 {
lab=gnd}
N 490 -200 490 -130 {
lab=gnd}
N 400 -200 490 -200 {
lab=gnd}
N 400 -130 490 -130 {
lab=gnd}
N 240 -420 240 -130 {
lab=gnd}
N 940 -200 960 -200 {
lab=clk}
C {iopin.sym} 1060 -930 0 0 {name=p1 lab=vdd}
C {iopin.sym} 1060 -130 0 0 {name=p2 lab=gnd}
C {ipin.sym} 440 -570 0 0 {name=p3 lab=v+}
C {ipin.sym} 860 -570 0 1 {name=p4 lab=v-}
C {ipin.sym} 550 -830 0 0 {name=p5 lab=vbias}
C {ipin.sym} 330 -200 0 0 {name=p6 lab=clk}
C {opin.sym} 1160 -470 0 0 {name=p7 lab=out-}
C {opin.sym} 140 -470 0 1 {name=p8 lab=out+}
C {lab_pin.sym} 650 -570 3 0 {name=p9 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 700 -740 2 0 {name=p10 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 630 -740 0 0 {name=M13
l=0.3u
w=18u
ng=3
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 630 -830 0 0 {name=M3
l=0.3u
w=18u
ng=3
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 470 -570 0 0 {name=M2
l=200n
w=32u
ng=4
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 830 -570 0 1 {name=M1
l=200n
w=32u
ng=4
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 1040 -530 0 0 {name=M4
l=0.200u
w=8u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 260 -530 0 1 {name=M5
l=0.200u
w=8u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 260 -420 2 0 {name=M11
l=0.200u
w=4.0u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 1040 -420 2 1 {name=M12
l=0.200u
w=4.0u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 600 -200 2 0 {name=M6
l=0.200u
w=4.0u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 380 -200 2 1 {name=M10
l=0.200u
w=4.0u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 920 -200 2 0 {name=M7
l=0.200u
w=4.0u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 700 -200 2 1 {name=M8
l=0.200u
w=4.0u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {lab_pin.sym} 960 -200 2 0 {name=p11 sig_type=std_logic lab=clk}

50
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/inverter.sch
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@ -1,50 +0,0 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 330 -280 370 -280 {lab=Vin}
N 330 -280 330 -190 {lab=Vin}
N 330 -190 370 -190 {lab=Vin}
N 410 -230 490 -230 {lab=Vout}
N 410 -230 410 -220 {lab=Vout}
N 410 -250 410 -230 {lab=Vout}
N 410 -160 410 -130 {lab=Gnd}
N 410 -340 410 -310 {lab=Vdd}
N 410 -280 520 -280 {lab=#net1}
N 410 -340 520 -340 {lab=Vdd}
N 410 -190 520 -190 {lab=#net2}
N 410 -130 520 -130 {lab=Gnd}
C {sg13g2_pr/sg13_lv_nmos.sym} 390 -190 2 1 {name=M1
l=0.45u
w=1.0u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 390 -280 0 0 {name=M2
l=0.45u
w=2.0u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {iopin.sym} 490 -230 2 1 {name=p2 lab=Vout}
C {iopin.sym} 410 -340 2 0 {name=p5 lab=Vdd}
C {iopin.sym} 330 -240 2 0 {name=p6 lab=Vin}
C {iopin.sym} 410 -130 2 0 {name=p1 lab=Gnd}
C {sg13g2_pr/ntap1.sym} 520 -310 0 0 {name=R1
model=ntap1
spiceprefix=X
w=0.78e-6
l=0.78e-6
}
C {sg13g2_pr/ptap1.sym} 520 -160 2 1 {name=R2
model=ptap1
spiceprefix=X
w=0.78e-6
l=0.78e-6
}

25
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/inverter.sym
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@ -1,25 +0,0 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 7 -70 -80 -70 -60 {}
L 7 -150 0 -130 0 {}
L 7 110 0 130 0 {}
L 7 -70 70 -70 90 {}
B 5 -72.5 -82.5 -67.5 -77.5 {name=Vdd dir=inout}
B 5 -152.5 -2.5 -147.5 2.5 {name=Vin dir=inout}
B 5 127.5 -2.5 132.5 2.5 {name=Vout dir=inout}
B 5 -72.5 87.5 -67.5 92.5 {name=Gnd dir=inout}
A 4 105 0 7.071067811865476 135 360 {}
P 4 5 100 0 -130 -80 -130 90 100 0 100 0 {}
T {@symname} -84 -6 0 0 0.3 0.3 {}
T {@name} -45 -32 0 0 0.2 0.2 {}
T {Vdd} -74 -55 3 1 0.2 0.2 {}
T {Vin} -125 -4 0 0 0.2 0.2 {}
T {Vout} 80 -9 0 1 0.2 0.2 {}
T {Gnd} -66 65 1 1 0.2 0.2 {}

68
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/inverter_tb.sch
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@ -1,68 +0,0 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
B 2 710 -550 1510 -150 {flags=graph
y1=-0.0023
y2=1.3
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=2e-06
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
node=vout
color=4
dataset=-1
unitx=1
logx=0
logy=0
}
N 150 -170 150 -140 {lab=Vin}
N 70 -170 70 -140 {lab=Vdd}
N 70 -80 70 -60 {lab=GND}
N 110 -60 150 -60 {lab=GND}
N 150 -80 150 -60 {lab=GND}
N 110 -60 110 -50 {lab=GND}
N 70 -60 110 -60 {lab=GND}
N 320 -410 320 -380 {lab=Vdd}
N 320 -210 320 -190 {lab=GND}
N 220 -300 240 -300 {lab=Vin}
N 520 -300 540 -300 {lab=Vout}
C {vsource.sym} 150 -110 0 0 {name=V1 value="PULSE(0 1.2 0.5u 10n 10n 1u 2u 1)" savecurrent=false}
C {vsource.sym} 70 -110 0 0 {name=V2 value=1.2 savecurrent=false}
C {gnd.sym} 110 -50 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 150 -170 0 0 {name=p1 sig_type=std_logic lab=Vin}
C {lab_pin.sym} 70 -170 0 0 {name=p3 sig_type=std_logic lab=Vdd}
C {code_shown.sym} 40 -540 0 0 {name=NGSPICE
only_toplevel=true
value="
.control
save all
tran 50n 2u
write test_inverter.raw
.endc
" }
C {devices/code_shown.sym} 280 -540 0 0 {name=MODEL only_toplevel=true
format="tcleval( @value )"
value="
.lib cornerMOSlv.lib mos_tt
.lib cornerRES.lib res_typ
"}
C {launcher.sym} 770 -120 0 0 {name=h5
descr="load waves"
tclcommand="xschem raw_read $netlist_dir/test_inverter.raw tran"
}
C {inverter.sym} 390 -300 0 0 {name=x1}
C {lab_pin.sym} 220 -300 0 0 {name=p2 sig_type=std_logic lab=Vin}
C {gnd.sym} 320 -190 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 320 -410 0 0 {name=p4 sig_type=std_logic lab=Vdd}
C {lab_pin.sym} 540 -300 0 1 {name=p5 sig_type=std_logic lab=Vout}

BIN
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/layout/inverter.gds
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10
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/layout/inverter_extracted.cir
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@ -1,10 +0,0 @@
* Extracted by KLayout with SG13G2 LVS runset on : 07/07/2025 16:12
.SUBCKT inverter Gnd Vout Vin Vdd
M$1 Gnd Vin Vout \$1 sg13_lv_nmos L=0.45u W=1u AS=0.34p AD=0.34p PS=2.68u
+ PD=2.68u
M$2 Vdd Vin Vout \$2 sg13_lv_pmos L=0.45u W=2u AS=0.68p AD=0.68p PS=4.68u
+ PD=4.68u
R$3 \$2 Vdd ntap1 A=0.6084p P=3.12u
R$4 \$1 Gnd ptap1 A=0.6084p P=3.12u
.ENDS inverter

0
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/inverter.nodes
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0
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/inverter.sim
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58
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/kpex.log
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@ -1,58 +0,0 @@
[2025-07-09 12:17:50,912] [INFO] GDS input file passed, running in LVS mode
[2025-07-09 12:17:50,914] [INFO] Found cell inverter in GDS ../layout/inverter.gds (only top cell)
[2025-07-09 12:17:50,920] [INFO] Calling MAGIC
[2025-07-09 12:17:50,921] [SUBPROCESS] magic -dnull -noconsole -rcfile /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/magic/ihp-sg13g2.magicrc ./pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl, output file: ./pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Output.txt
[2025-07-09 12:17:50,939] [SUBPROCESS]
[2025-07-09 12:17:50,940] [SUBPROCESS] Magic 8.3 revision 530 - Compiled on Mo 7. Jul 14:09:23 CEST 2025.
[2025-07-09 12:17:50,941] [SUBPROCESS] Starting magic under Tcl interpreter
[2025-07-09 12:17:50,942] [SUBPROCESS] Using the terminal as the console.
[2025-07-09 12:17:50,942] [SUBPROCESS] Using NULL graphics device.
[2025-07-09 12:17:50,974] [SUBPROCESS] Processing system .magicrc file
[2025-07-09 12:17:50,981] [SUBPROCESS] Sourcing design .magicrc for technology ihp-sg13g2 ...
[2025-07-09 12:17:50,982] [SUBPROCESS] 2 Magic internal units = 1 Lambda
[2025-07-09 12:17:51,003] [SUBPROCESS] Input style sg13g2(): scaleFactor=2, multiplier=2
[2025-07-09 12:17:51,101] [SUBPROCESS] The following types are not handled by extraction and will be treated as non-electrical types:
[2025-07-09 12:17:51,102] [SUBPROCESS] fillfet sealcont difffill nemitter hvnemitter hvisodiffres sealvia1 sealvia2 sealvia3 sealvia4 sealvia5 sealvia6 pad seal thruvia
[2025-07-09 12:17:51,105] [SUBPROCESS] Scaled tech values by 2 / 1 to match internal grid scaling
[2025-07-09 12:17:51,106] [SUBPROCESS] Loading "./pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl" from command line.
[2025-07-09 12:17:51,106] [SUBPROCESS] Warning: Calma reading is not undoable! I hope that's OK.
[2025-07-09 12:17:51,107] [SUBPROCESS] Library written using GDS-II Release 6.0
[2025-07-09 12:17:51,108] [SUBPROCESS] Library name: LIB
[2025-07-09 12:17:51,108] [SUBPROCESS] Reading "$$$CONTEXT_INFO$$$".
[2025-07-09 12:17:51,108] [SUBPROCESS] Reading "nmos".
[2025-07-09 12:17:51,109] [SUBPROCESS] Reading "ptap1".
[2025-07-09 12:17:51,109] [SUBPROCESS] Making label "sub!" on type isosubstrate in cell ptap1 sticky.
[2025-07-09 12:17:51,110] [SUBPROCESS] Reading "ntap1".
[2025-07-09 12:17:51,110] [SUBPROCESS] Reading "pmos$1".
[2025-07-09 12:17:51,111] [SUBPROCESS] Reading "inverter".
[2025-07-09 12:17:51,113] [SUBPROCESS] Extracting inverter into /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter.ext:
[2025-07-09 12:17:51,114] [SUBPROCESS] Port: name = Vout is new node 0x6202078064b0
[2025-07-09 12:17:51,114] [SUBPROCESS] Location is (266, -211); drivepoint (266, -211)
[2025-07-09 12:17:51,115] [SUBPROCESS] Port: name = Vin is new node 0x62020780a810
[2025-07-09 12:17:51,116] [SUBPROCESS] Location is (95, -213); drivepoint (95, -213)
[2025-07-09 12:17:51,116] [SUBPROCESS] Port: name = Gnd is new node 0x6202079978f0
[2025-07-09 12:17:51,117] [SUBPROCESS] Location is (20, -732); drivepoint (20, -732)
[2025-07-09 12:17:51,117] [SUBPROCESS] Port: name = Vdd is new node 0x62020818bf70
[2025-07-09 12:17:51,118] [SUBPROCESS] Location is (-205, 318); drivepoint (-205, 318)
[2025-07-09 12:17:51,118] [SUBPROCESS] Total Nets: 4
[2025-07-09 12:17:51,119] [SUBPROCESS] Nets extracted: 4 (1.000000)
[2025-07-09 12:17:51,119] [SUBPROCESS] Nets output: 4 (1.000000)
[2025-07-09 12:17:51,120] [SUBPROCESS] Devs merged: 0
[2025-07-09 12:17:51,120] [SUBPROCESS] exttospice finished.
[2025-07-09 12:17:51,121] [INFO] MAGIC succeeded after 0.1993s
[2025-07-09 12:17:51,127] [SUBPROCESS] Report DB saved at: ./pex_output/inverter__inverter/magic_RC/inverter_MAGIC_report.rdb.gz
[2025-07-09 12:17:51,128] [SUBPROCESS] SPICE netlist saved at: ./pex_output/inverter__inverter/magic_RC/inverter.pex.spice
[2025-07-09 12:17:51,129] [SUBPROCESS] * NGSPICE file created from inverter.ext - technology: ihp-sg13g2
.subckt inverter Vout Vin Gnd Vdd
X0 Vout Vin Vdd Vdd sg13_lv_pmos ad=0.68p pd=4.68u as=0.68p ps=4.68u w=2u l=0.45u
X1 Vout Vin Gnd Gnd sg13_lv_nmos ad=0.34p pd=2.68u as=0.34p ps=2.68u w=1u l=0.45u
C0 Vdd Vin 0.14482f
C1 Vout Vdd 0.13155f
C2 Vout Vin 0.10077f
R0 Vin Vin.n0 7.52248
C3 Vout Gnd 0.39245f
C4 Vin Gnd 0.64666f
C5 Vdd Gnd 0.15308f
.ends

58
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@ -1,58 +0,0 @@
GDS input file passed, running in LVS mode
Found cell inverter in GDS ../layout/inverter.gds (only top cell)
Calling MAGIC
magic -dnull -noconsole -rcfile /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/magic/ihp-sg13g2.magicrc ./pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl, output file: ./pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Output.txt
Magic 8.3 revision 530 - Compiled on Mo 7. Jul 14:09:23 CEST 2025.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology ihp-sg13g2 ...
2 Magic internal units = 1 Lambda
Input style sg13g2(): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
fillfet sealcont difffill nemitter hvnemitter hvisodiffres sealvia1 sealvia2 sealvia3 sealvia4 sealvia5 sealvia6 pad seal thruvia
Scaled tech values by 2 / 1 to match internal grid scaling
Loading "./pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl" from command line.
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "$$$CONTEXT_INFO$$$".
Reading "nmos".
Reading "ptap1".
Making label "sub!" on type isosubstrate in cell ptap1 sticky.
Reading "ntap1".
Reading "pmos$1".
Reading "inverter".
Extracting inverter into /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter.ext:
Port: name = Vout is new node 0x6202078064b0
Location is (266, -211); drivepoint (266, -211)
Port: name = Vin is new node 0x62020780a810
Location is (95, -213); drivepoint (95, -213)
Port: name = Gnd is new node 0x6202079978f0
Location is (20, -732); drivepoint (20, -732)
Port: name = Vdd is new node 0x62020818bf70
Location is (-205, 318); drivepoint (-205, 318)
Total Nets: 4
Nets extracted: 4 (1.000000)
Nets output: 4 (1.000000)
Devs merged: 0
exttospice finished.
MAGIC succeeded after 0.1993s
Report DB saved at: ./pex_output/inverter__inverter/magic_RC/inverter_MAGIC_report.rdb.gz
SPICE netlist saved at: ./pex_output/inverter__inverter/magic_RC/inverter.pex.spice
* NGSPICE file created from inverter.ext - technology: ihp-sg13g2
.subckt inverter Vout Vin Gnd Vdd
X0 Vout Vin Vdd Vdd sg13_lv_pmos ad=0.68p pd=4.68u as=0.68p ps=4.68u w=2u l=0.45u
X1 Vout Vin Gnd Gnd sg13_lv_nmos ad=0.34p pd=2.68u as=0.34p ps=2.68u w=1u l=0.45u
C0 Vdd Vin 0.14482f
C1 Vout Vdd 0.13155f
C2 Vout Vin 0.10077f
R0 Vin Vin.n0 7.52248
C3 Vout Gnd 0.39245f
C4 Vin Gnd 0.64666f
C5 Vdd Gnd 0.15308f
.ends

23
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@ -1,23 +0,0 @@
timestamp 0
version 8.3
tech ihp-sg13g2
style ngspice()
scale 1000 1 0.5
resistclasses 3000000 67000 110 88 88 88 88 18 11
parameters sg13_lv_nmos l=l w=w a1=as p1=ps a2=ad p2=pd
parameters sg13_lv_pmos l=l w=w a1=as p1=ps a2=ad p2=pd
port "Vout" 2 266 -211 298 -173 m1
port "Vin" 3 95 -213 127 -175 m1
port "Vdd" 5 -205 318 -173 356 m1
port "Gnd" 4 20 -732 52 -694 m1
node "ptap1_0.sub!" 0 0 28 -796 isosub 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "Vout" 1 392.446 266 -211 m1 0 0 0 0 91916 2354 0 0 0 0 0 0 0 0 0 0 0 0
node "Vin" 0 646.659 95 -213 m1 0 0 0 0 13590 482 0 0 0 0 0 0 0 0 0 0 0 0
node "Vdd" 1 153.076 -205 318 m1 0 0 0 0 42800 1364 0 0 0 0 0 0 0 0 0 0 0 0
equiv "Vdd" "ntap1_0.well"
substrate "Gnd" 0 0 20 -732 m1 0 0 0 0 21536 1036 0 0 0 0 0 0 0 0 0 0 0 0
cap "Vdd" "Vin" 144.819
cap "Vdd" "Vout" 131.55
cap "Vout" "Vin" 100.772
device msubckt sg13_lv_nmos 67 -562 68 -561 l=90 w=200 "Gnd" "Vin" 180 0 "Gnd" 200 13600,536 "Vout" 200 13600,536
device msubckt sg13_lv_pmos 67 9 68 10 l=90 w=400 "Vdd" "Vin" 180 0 "Vdd" 400 27200,936 "Vout" 400 27200,936

9
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter.res.ext
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@ -1,9 +0,0 @@
scale 1000 1 0.5
rnode "Vdd" 0 -0 -205 318 0
rnode "ntap1_0.well" 0 0 -63 345 0
resist "ntap1_0.well" "Vdd" 8.51657
rnode "Gnd" 0 0 20 -732 0
rnode "Vin.n0" 0 0 111 -158 0
rnode "Vin" 0 0 95 -213 0
resist "Vin" "Vin.n0" 7.52198
rnode "Vout" 0 0 266 -211 0

27
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl
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@ -1,27 +0,0 @@
# Generated by kpex 0.2.7
crashbackups stop
drc off
gds read /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/layout/inverter.gds
load inverter
select top cell
flatten inverter_flat
load inverter_flat
cellname delete inverter -noprompt
cellname rename inverter_flat inverter
select top cell
extract path /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/magic_RC
extract do resistance
extract all
ext2sim labels on
ext2sim
extresist tolerance 1
extresist all
ext2spice short resistor
ext2spice merge conservative
ext2spice cthresh 0.02
ext2spice rthresh 50
ext2spice extresist on
ext2spice subcircuits top on
ext2spice format ngspice
ext2spice -p /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/magic_RC -o /home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter.pex.spice
quit -noprompt

BIN
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter_MAGIC_report.rdb.gz
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#!/bin/bash
set -e
###############################################################################
# ⬇⬇⬇ USER CONFIGURATION ⬇⬇⬇ #
###############################################################################
# Activate Python environment (adjust this path to your Python venv activate script) Or if you python version is >3.12 ignore asuming klayout_pex is installed
PYTHON_ENV="$HOME/misc/klayout_pex/bin/activate"
# Example: /home/username/misc/klayout_pex/bin/activate
# Path to Magic executable used by kpex (adjust if installed elsewhere)
KPEX_MAGIC_EXE="$HOME/.local/bin/magic"
# Example: /usr/local/bin/magic or ~/.local/bin/magic
# Cell and schematic names (do NOT include file extensions)
CELL_NAME="inverter" # The name of your top cell / device under test (DUT)
TESTBENCH_NAME="inverter_tb" # Name of your testbench schematic (without extension)
# Paths relative to this script or absolute paths
SPICE_DIR="../simulations" # Directory containing netlist/spice files for testbench
LAYOUT_DIR="../layout" # Directory containing layout files (.gds etc.)
# Important: Path to your PDK root directory must be set externally in env variable PDK_ROOT
PDK_NAME="ihp_sg13g2" # Your PDK name (must match PDK_ROOT contents)
MAGICRC="$PDK_ROOT/$PDK/libs.tech/magic/ihp-sg13g2.magicrc"
# The magicrc file for your PDK, used during extraction
# Path to your testbench schematic file (relative or absolute)
# You can override this here if your schematic is located elsewhere
TESTBENCH_PATH="../${TESTBENCH_NAME}.sch"
##############################################################################################################################################################
# ⛔ DO NOT TOUCH BELOW THIS LINE ⛔ Unless you see clear issue with your setup :) #
##############################################################################################################################################################
# Derived paths based on above variables
LAYOUT_GDS="${LAYOUT_DIR}/${CELL_NAME}.gds"
REFERENCE_SPICE="${SPICE_DIR}/${TESTBENCH_NAME}.spice"
# Check if required files exist before proceeding
if [[ ! -f "$PYTHON_ENV" ]]; then
echo "[ERROR] Python environment activate script not found: $PYTHON_ENV"
exit 1
fi
if [[ ! -x "$KPEX_MAGIC_EXE" ]]; then
echo "[ERROR] Magic executable not found or not executable: $KPEX_MAGIC_EXE"
exit 1
fi
if [[ ! -f "$LAYOUT_GDS" ]]; then
echo "[ERROR] Layout GDS file not found: $LAYOUT_GDS"
exit 1
fi
if [[ ! -f "$REFERENCE_SPICE" ]]; then
echo "[ERROR] Reference spice file not found: $REFERENCE_SPICE"
exit 1
fi
if [[ ! -f "$TESTBENCH_PATH" ]]; then
echo "[ERROR] Testbench schematic file not found: $TESTBENCH_PATH"
exit 1
fi
if [[ ! -f "$MAGICRC" ]]; then
echo "[ERROR] Magicrc file for PDK not found: $MAGICRC"
exit 1
fi
# Activate Python virtual environment
echo "[INFO] Activating Python environment..."
source "$PYTHON_ENV"
echo "[INFO] Using MAGIC executable: $KPEX_MAGIC_EXE"
# Run parasitic extraction with kpex
echo "[INFO] Running parasitic extraction with KPEX..."
kpex \
--pdk "$PDK_NAME" \
--magic \
--gds "$LAYOUT_GDS" \
--schematic "$REFERENCE_SPICE" \
--cell "$CELL_NAME" \
--magicrc "$MAGICRC" \
--magic_mode RC \
--magic_cthresh 0.02 \
--magic_rthresh 50 \
--magic_short resistor \
--magic_merge conservative \
--out_dir ./pex_output
# Create working directory for schematic updates if not exists
mkdir -p xschem
# Find the generated spice file (assuming only one)
spice_location=$(find ./pex_output -type f -name "*.spice" | head -n 1)
if [[ -z "$spice_location" ]]; then
echo "[ERROR] No .spice file found in pex_output directory"
exit 1
fi
echo "[INFO] Found extracted spice file: $spice_location"
# Run Python script to fix port ordering in the extracted netlist
echo "[INFO] Reordering subcircuit pins to match original schematic..."
python3 scripts/match_subckt_order.py "$spice_location" "$REFERENCE_SPICE"
# Enter schematic directory
cd xschem || { echo "[ERROR] Failed to enter xschem directory"; exit 1; }
# Run python script to update schematic with PEX subcircuit
echo "[INFO] Updating schematic with PEX subcircuit..."
python3 ../scripts/insert_pex_subckt.py "../$TESTBENCH_PATH" "../$spice_location" # remark this is relatives path native to my setup
# Generate xschemrc file pointing to schematic and symbol folders
# Adjust this path if your schematic/symbols are elsewhere
XSCHEM_PATH="../../" # relative to current 'xschem' folder (points to symbol for the DUT)
echo "[INFO] Generating xschemrc file..."
python3 ../scripts/xschem_rc.py "$XSCHEM_PATH"
echo "[✅ DONE] Modified schematic generated and saved in: $(pwd)/"

123
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/scripts/insert_pex_subckt.py
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@ -1,123 +0,0 @@
import sys
import os
def load_text_file(file_path):
with open(file_path, 'r') as f:
return f.read()
def save_text_file(file_path, text):
with open(file_path, 'w') as f:
f.write(text)
def read_spice_definition(spice_path):
with open(spice_path, "r") as f:
lines = f.readlines()
subckt_line_index = next((i for i, line in enumerate(lines) if line.strip().lower().startswith(".subckt")), None)
if subckt_line_index is None:
raise ValueError(f"No .subckt line found in SPICE file: {spice_path}")
parts = lines[subckt_line_index].strip().split()
subckt_name = parts[1]
new_subckt_name = subckt_name
parts[1] = new_subckt_name
lines[subckt_line_index] = ' '.join(parts) + '\n'
definition_lines = []
recording = False
for line in lines:
if line.strip().lower().startswith(".subckt"):
recording = True
if recording:
definition_lines.append(line.rstrip())
if line.strip().lower() == ".ends":
break
return new_subckt_name, '\n'.join(definition_lines)
def find_subckt_location(subckt_name, schematic_file):
text_content = load_text_file(schematic_file)
return text_content.find(subckt_name + '.sym')
def find_first_curly_brackets_span(text, start_pos):
open_pos = text.find('{', start_pos)
if open_pos == -1:
return None, None
depth = 1
for i in range(open_pos + 1, len(text)):
if text[i] == '{':
depth += 1
elif text[i] == '}':
depth -= 1
if depth == 0:
return open_pos, i
return None, None
def replace_curly_brackets_content(text, start_idx, end_idx, new_content, subckt_name):
content = text[start_idx+1:end_idx].strip('\n ')
lines = content.splitlines()
name_line_index = next((i for i, line in enumerate(lines) if line.strip().startswith("name=")), None)
schematic_line = "schematic=" + subckt_name
if name_line_index is None:
new_lines = ['spice_sym_def="', new_content.strip(), '"'] + lines
else:
new_lines = (
lines[:name_line_index+1] +
[schematic_line] +
['spice_sym_def="', new_content.strip(), '"'] +
lines[name_line_index+1:]
)
return text[:start_idx+1] + '\n' + '\n'.join(new_lines) + '\n' + text[end_idx:]
def process_pair(spice_path, schematic_path):
print(f"\nProcessing:\n SPICE: {spice_path}\n Schematic: {schematic_path}")
try:
subckt_name, definition = read_spice_definition(spice_path)
print(f" Subcircuit name: {subckt_name}")
except Exception as e:
print(f" Error reading spice file: {e}")
return
# If subckt_name ends with '_pex', strip it for schematic search
search_subckt_name = subckt_name
if subckt_name.endswith("_pex"):
search_subckt_name = subckt_name[:-4]
location = find_subckt_location(search_subckt_name, schematic_path)
if location == -1:
print(f" '{search_subckt_name}.sym' not found in schematic file.")
return
schematic_content = load_text_file(schematic_path)
start_idx, end_idx = find_first_curly_brackets_span(schematic_content, location)
if start_idx is None:
print(" No matching curly brackets found after .sym device.")
return
new_schematic_content = replace_curly_brackets_content(
schematic_content, start_idx, end_idx, definition, subckt_name
)
# Save the file in the current working directory (where script is run)
base_name = os.path.basename(schematic_path)
name, ext = os.path.splitext(base_name)
new_filename = os.path.join(os.getcwd(), f"{name}_pex{ext}")
save_text_file(new_filename, new_schematic_content)
print(f" Replacement done and new schematic file saved as:\n {new_filename}")
if __name__ == "__main__":
if len(sys.argv) != 3:
print("Usage:\n python3 script.py <schematic.sch> <spice_file.spice>")
sys.exit(1)
schematic = sys.argv[1]
spice_path = sys.argv[2]
print(f"Starting processing with schematic='{schematic}', spice='{spice_path}'") # Debug print
process_pair(spice_path, schematic)

61
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/scripts/match_subckt_order.py
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@ -1,61 +0,0 @@
import sys
import re
from pathlib import Path
def get_original_io_order(original_netlist_path):
io_pins = []
with open(original_netlist_path, "r") as f:
for line in f:
stripped = line.strip()
# Look for .subckt line (not commented out)
if stripped.startswith(".subckt"):
tokens = stripped.split()
# tokens[0] = '.subckt', tokens[1] = subckt name, rest are pins
if len(tokens) >= 3:
io_pins = tokens[2:]
break
if not io_pins:
raise ValueError("Could not find IO pins in original schematic")
return io_pins
def reorder_pex_subckt(pex_path, correct_order):
with open(pex_path, "r") as f:
lines = f.readlines()
new_lines = []
subckt_found = False
for line in lines:
if line.strip().startswith(".subckt") and not subckt_found:
tokens = line.strip().split()
subckt_name = tokens[1]
ports = tokens[2:]
if set(ports) != set(correct_order):
raise ValueError("Port names in PEX netlist don't match original IO pins")
# Create new subckt line with reordered ports
reordered_line = ".subckt " + subckt_name +"_pex"+" " + " ".join(correct_order) + "\n"
new_lines.append(reordered_line)
subckt_found = True
else:
new_lines.append(line)
with open(pex_path, "w") as f:
f.writelines(new_lines)
print(f"Rewrote subckt line in {pex_path}")
if __name__ == "__main__":
if len(sys.argv) != 3:
print("Usage: python patch_pex_order.py <pex_spice_path> <original_schematic_spice_path>")
sys.exit(1)
pex_spice = Path(sys.argv[1])
original_schematic = Path(sys.argv[2])
io_order = get_original_io_order(original_schematic)
reorder_pex_subckt(pex_spice, io_order)

37
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/scripts/xschem_rc.py
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@ -1,37 +0,0 @@
import sys
def generate_xschemrc(custom_paths):
lines = [
"# xschemrc - Custom configuration file for xschem",
"# This file sources another xschemrc file from a known location",
"",
"# Source the base configuration from a known location",
"source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc",
"",
"# (Optional) Add any custom overrides or extensions below",
'# set xschem_library_path /home/user/my_libs',
'# set xschem_gui_font "Monospace 10"',
"",
"append XSCHEM_LIBRARY_PATH :$PDK_ROOT/ihp-sg13g2/libs.tech/xschem"
]
# Append each custom path with the prefix "../"
for path in custom_paths:
lines.append(f"append XSCHEM_LIBRARY_PATH :{path}")
return "\n".join(lines) + "\n"
def main():
if len(sys.argv) < 2:
print("Usage: python3 make_xschemrc.py <path1> [<path2> ... <pathN>]")
sys.exit(1)
custom_paths = sys.argv[1:]
content = generate_xschemrc(custom_paths)
with open("xschemrc", "w") as f:
f.write(content)
print(f"xschemrc file generated with {len(custom_paths)} custom paths.")
if __name__ == "__main__":
main()

84
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/xschem/inverter_tb_pex.sch
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@ -1,84 +0,0 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
B 2 710 -550 1510 -150 {flags=graph
y1=-0.0023
y2=1.3
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=2e-06
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
node=vout
color=4
dataset=-1
unitx=1
logx=0
logy=0
}
N 150 -170 150 -140 {lab=Vin}
N 70 -170 70 -140 {lab=Vdd}
N 70 -80 70 -60 {lab=GND}
N 110 -60 150 -60 {lab=GND}
N 150 -80 150 -60 {lab=GND}
N 110 -60 110 -50 {lab=GND}
N 70 -60 110 -60 {lab=GND}
N 320 -410 320 -380 {lab=Vdd}
N 320 -210 320 -190 {lab=GND}
N 220 -300 240 -300 {lab=Vin}
N 520 -300 540 -300 {lab=Vout}
C {vsource.sym} 150 -110 0 0 {name=V1 value="PULSE(0 1.2 0.5u 10n 10n 1u 2u 1)" savecurrent=false}
C {vsource.sym} 70 -110 0 0 {name=V2 value=1.2 savecurrent=false}
C {gnd.sym} 110 -50 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 150 -170 0 0 {name=p1 sig_type=std_logic lab=Vin}
C {lab_pin.sym} 70 -170 0 0 {name=p3 sig_type=std_logic lab=Vdd}
C {code_shown.sym} 40 -540 0 0 {name=NGSPICE
only_toplevel=true
value="
.control
save all
tran 50n 2u
write test_inverter.raw
.endc
" }
C {devices/code_shown.sym} 280 -540 0 0 {name=MODEL only_toplevel=true
format="tcleval( @value )"
value="
.lib cornerMOSlv.lib mos_tt
.lib cornerRES.lib res_typ
"}
C {launcher.sym} 770 -120 0 0 {name=h5
descr="load waves"
tclcommand="xschem raw_read $netlist_dir/test_inverter.raw tran"
}
C {inverter.sym} 390 -300 0 0 {
name=x1
schematic=inverter_pex
spice_sym_def="
.subckt inverter_pex Vdd Vin Vout Gnd
X0 Vout Vin Vdd Vdd sg13_lv_pmos ad=0.68p pd=4.68u as=0.68p ps=4.68u w=2u l=0.45u
X1 Vout Vin Gnd Gnd sg13_lv_nmos ad=0.34p pd=2.68u as=0.34p ps=2.68u w=1u l=0.45u
C0 Vdd Vin 0.14482f
C1 Vout Vdd 0.13155f
C2 Vout Vin 0.10077f
R0 Vin Vin.n0 7.52248
C3 Vout Gnd 0.39245f
C4 Vin Gnd 0.64666f
C5 Vdd Gnd 0.15308f
.ends
"
}
C {lab_pin.sym} 220 -300 0 0 {name=p2 sig_type=std_logic lab=Vin}
C {gnd.sym} 320 -190 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 320 -410 0 0 {name=p4 sig_type=std_logic lab=Vdd}
C {lab_pin.sym} 540 -300 0 1 {name=p5 sig_type=std_logic lab=Vout}

12
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/pex/xschem/xschemrc
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@ -1,12 +0,0 @@
# xschemrc - Custom configuration file for xschem
# This file sources another xschemrc file from a known location
# Source the base configuration from a known location
source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
# (Optional) Add any custom overrides or extensions below
# set xschem_library_path /home/user/my_libs
# set xschem_gui_font "Monospace 10"
append XSCHEM_LIBRARY_PATH :$PDK_ROOT/ihp-sg13g2/libs.tech/xschem
append XSCHEM_LIBRARY_PATH :../../

18
modules/module_3_8_bit_SAR_ADC/part_5_layout/components/inverter_example/xschemrc
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@ -1,18 +0,0 @@
# xschemrc - Custom configuration file for xschem
# This file sources another xschemrc file from a known location
# Source the base configuration from a known location
source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
# (Optional) Add any custom overrides or extensions below
# set xschem_library_path /home/user/my_libs
# set xschem_gui_font "Monospace 10"
#### include skywater libraries. Here I use [pwd]. This works if I start xschem from here.
###only if you dont have this setup already ###
###append XSCHEM_LIBRARY_PATH :[file dirname [info script]]
#### Add custom libraries (directories with .lib files)
append XSCHEM_LIBRARY_PATH :$PDK_ROOT/ihp-sg13g2/libs.tech/xschem