Merge c7b7042515 into 98cdc3d18d

modules/module_3_8_bit_SAR_ADC/part_1_comparator/README.md

@@ -159,7 +159,6 @@ As you can see, this setup closely resembles the testbench used for the simple t
 
 ```
 name=V2 value="PULSE(595e-3 605e-3 0 tr 1S 1S)"
-
 ```
 
 Looking at the model includes, we see that now have defined the mismatch model

modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/offset_MC_analysis.sch

@@ -1,8 +1,9 @@
-v {xschem version=3.4.6 file_version=1.2}
+v {xschem version=3.4.8RC file_version=1.3}
 G {}
 K {}
 V {}
 S {}
+F {}
 E {}
 N -540 -180 -540 -160 {
 lab=vbias}
@@ -102,11 +103,9 @@ footprint=1206
 device="ceramic capacitor"}
 C {gnd.sym} 460 -140 0 0 {name=l6 lab=GND}
 C {gnd.sym} 460 -300 2 0 {name=l7 lab=GND}
-C {devices/code_shown.sym} -675 -780 0 0 {name=NGSPICE1 only_toplevel=false 
+C {devices/code_shown.sym} -675 -790 0 0 {name=NGSPICE only_toplevel=false 
 value="
-.lib cornerCAP.lib cap_typ
-.lib cornerMOSlv.lib mos_tt_stat
-
+.param mm_ok=1
 .control
   let run = 1
   let mc_runs = 100
@@ -136,5 +135,5 @@ C {dynamic_comparator.sym} 270 -220 0 0 {name=x1}
 C {devices/code_shown.sym} -5 -580 0 0 {name=MODEL only_toplevel=false
 format="tcleval( @value )"
 value="
-.lib cornerMOSlv.lib mos_tt_stat
+.lib cornerMOSlv.lib mos_tt_mismatch
 "}

modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/README.md

@@ -9,14 +9,13 @@ Before diving into the full ADC schematic, it's essential to check whether the S
 
 > ⚠️ **Note:** Make sure to copy the shared object file (`.so`) and place it relative to the testbench, just like we did before. Create a simulation folder and include it there:
 
-
+```
 ├── SAR_ADC_tb.sch
 ├── sar_adc_tutorial.sch
 ├── simulations
-
 │   └── sar_logic.so
-
 └── xschemrc
+```
 
 In this example, the wiring looks like this:
 <p align="center">