SAC_ADC comparator readme typos

2026-02-26 13:45:08 +00:00 · 2026-02-26 13:45:08 +00:00 · c7b7042515
parent 7476dadf8b
commit c7b7042515
1 changed files with 0 additions and 1 deletions
--- a/modules/module_3_8_bit_SAR_ADC/part_1_comparator/README.md
+++ b/modules/module_3_8_bit_SAR_ADC/part_1_comparator/README.md
@ -159,7 +159,6 @@ As you can see, this setup closely resembles the testbench used for the simple t

 ```
 name=V2 value="PULSE(595e-3 605e-3 0 tr 1S 1S)"
-
 ```

 Looking at the model includes, we see that now have defined the mismatch model