push new utils for kpex
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PhillipRambo
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b0836ebcc2
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b5cccf4f55
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#!/bin/bash
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set -e
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# Hardcoded paths (except PDK stuff)
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LAYOUT_PATH="../layout/inverter.gds"
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SCHEMATIC="../simulations/inverter.spice"
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PDK_NAME="ihp_sg13g2"
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MAGICRC="$PDK_ROOT/$PDK/libs.tech/magic/ihp-sg13g2.magicrc" # The magicrc file for your PDK, used during extraction
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# Run parasitic extraction with kpex
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kpex \
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--pdk "$PDK_NAME" \
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--magic \
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--schematic "$SCHEMATIC" \
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--gds "$LAYOUT_PATH" \
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--magicrc "$MAGICRC" \
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--magic_mode RC \
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--magic_cthresh 0.02 \
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--magic_rthresh 50 \
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--magic_short resistor \
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--magic_merge conservative \
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--out_dir ./pex_output
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timestamp 0
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version 8.3
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tech ihp-sg13g2
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style ngspice()
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scale 1000 1 0.5
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resistclasses 3000000 67000 110 88 88 88 88 18 11
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parameters sg13_lv_nmos l=l w=w a1=as p1=ps a2=ad p2=pd
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parameters sg13_lv_pmos l=l w=w a1=as p1=ps a2=ad p2=pd
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port "Vout" 2 266 -211 298 -173 m1
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port "Vin" 3 95 -213 127 -175 m1
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port "Vdd" 5 -205 318 -173 356 m1
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port "Gnd" 4 20 -732 52 -694 m1
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node "ptap1_0.sub!" 0 0 28 -796 isosub 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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node "Vout" 1 392.446 266 -211 m1 0 0 0 0 91916 2354 0 0 0 0 0 0 0 0 0 0 0 0
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node "Vin" 0 646.659 95 -213 m1 0 0 0 0 13590 482 0 0 0 0 0 0 0 0 0 0 0 0
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node "Vdd" 1 153.076 -205 318 m1 0 0 0 0 42800 1364 0 0 0 0 0 0 0 0 0 0 0 0
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equiv "Vdd" "ntap1_0.well"
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substrate "Gnd" 0 0 20 -732 m1 0 0 0 0 21536 1036 0 0 0 0 0 0 0 0 0 0 0 0
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cap "Vout" "Vdd" 131.55
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cap "Vout" "Vin" 100.772
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cap "Vin" "Vdd" 144.819
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device msubckt sg13_lv_nmos 67 -562 68 -561 l=90 w=200 "Gnd" "Vin" 180 0 "Gnd" 200 13600,536 "Vout" 200 13600,536
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device msubckt sg13_lv_pmos 67 9 68 10 l=90 w=400 "Vdd" "Vin" 180 0 "Vdd" 400 27200,936 "Vout" 400 27200,936
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scale 1000 1 0.5
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# Generated by kpex 0.3.6
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crashbackups stop
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drc off
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gds read /home/pedersen/projects/IHP-AnalogAcademy/utils/PEX_Demo/layout/inverter.gds
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load inverter
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select top cell
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flatten inverter_flat
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load inverter_flat
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cellname delete inverter -noprompt
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cellname rename inverter_flat inverter
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select top cell
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extract path /home/pedersen/projects/IHP-AnalogAcademy/utils/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC
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extract all
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ext2sim labels on
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ext2sim
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extresist tolerance 1
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extresist all
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ext2spice short resistor
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ext2spice merge conservative
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ext2spice cthresh 0.02
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ext2spice extresist on
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ext2spice subcircuits top on
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ext2spice format ngspice
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ext2spice -p /home/pedersen/projects/IHP-AnalogAcademy/utils/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC -o /home/pedersen/projects/IHP-AnalogAcademy/utils/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter.pex.spice
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quit -noprompt
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Binary file not shown.
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timestamp 0
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version 8.3
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tech ihp-sg13g2
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style ngspice()
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scale 1000 1 0.5
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resistclasses 3000000 67000 110 88 88 88 88 18 11
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parameters sg13_lv_nmos l=l w=w a1=as p1=ps a2=ad p2=pd
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parameters sg13_lv_pmos l=l w=w a1=as p1=ps a2=ad p2=pd
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port "Vout" 3 266 -211 298 -173 m1
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port "Vin" 4 95 -213 127 -175 m1
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port "Vdd" 6 -237 285 -137 405 m1
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port "well" 2 -265 267 -109 423 nw
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port "Gnd" 5 -22 -770 78 -670 m1
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node "sub!" 0 0 28 -796 isosub 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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node "Vout" 1 392.446 266 -211 m1 0 0 0 0 91916 2354 0 0 0 0 0 0 0 0 0 0 0 0
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node "Vin" 0 646.659 95 -213 m1 0 0 0 0 13590 482 0 0 0 0 0 0 0 0 0 0 0 0
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node "Vdd" 1 153.076 -237 285 m1 0 0 0 0 42800 1364 0 0 0 0 0 0 0 0 0 0 0 0
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equiv "Vdd" "well"
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substrate "Gnd" 0 0 -22 -770 m1 0 0 0 0 21536 1036 0 0 0 0 0 0 0 0 0 0 0 0
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cap "Vout" "Vdd" 131.55
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cap "Vout" "Vin" 100.772
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cap "Vdd" "Vin" 144.819
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device msubckt sg13_lv_nmos 67 -562 68 -561 l=90 w=200 "Gnd" "Vin" 180 0 "Gnd" 200 13600,536 "Vout" 200 13600,536
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device msubckt sg13_lv_pmos 67 9 68 10 l=90 w=400 "Vdd" "Vin" 180 0 "Vdd" 400 27200,936 "Vout" 400 27200,936
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scale 1000 1 0.5
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rnode "well" 0 0 -265 267 0
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rnode "Vdd" 0 -0 -237 285 0
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resist "Vdd" "well" 8.53119
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rnode "Gnd.t1" 0 0 29 -462 0
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rnode "Gnd.t0" 0 0 112 -462 0
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rnode "Gnd.n0" 0 0 62 -754 0
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rnode "Gnd" 0 0 -22 -770 0
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resist "Gnd" "Gnd.n0" 0.055709
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resist "Gnd.n0" "Gnd.t1" 6.307
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resist "Gnd.n0" "Gnd.t0" 1079.19
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rnode "Vout.t1" 0 0 195 311 0
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rnode "Vout.t0" 0 0 195 -462 0
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rnode "Vout" 0 0 266 -211 0
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resist "Vout" "Vout.t1" 3.28762
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resist "Vout" "Vout.t0" 6.19274
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rnode "Vdd" 0 0 -237 285 0
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rnode "Vdd.t0" 0 0 29 379 0
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rnode "Vdd.n0" 0 0 -153 379 0
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rnode "well" 0 0 112 209 0
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resist "Vdd.n0" "Vdd" 0.0465926
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resist "Vdd.n0" "Vdd.t0" 3.18546
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resist "well" "Vdd.n0" 8.48516
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rnode "Vin.t0" 0 0 111 -158 0
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rnode "Vin" 0 0 95 -213 0
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resist "Vin" "Vin.t0" 7.52198
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device msubckt sg13_lv_nmos 67 -562 68 -561 "Gnd.t0" "Vin.t0" 180 0 "Gnd.t1" 200 13600,536 "Vout.t0" 200 13600,536
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device msubckt sg13_lv_pmos 67 9 68 10 "well" "Vin.t0" 180 0 "Vdd.t0" 400 27200,936 "Vout.t1" 400 27200,936
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# Generated by kpex 0.3.7
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crashbackups stop
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drc off
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gds read /home/pedersen/misc/inverter_example/layout/inverter_flat.gds
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load inverter
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select top cell
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flatten inverter_flat
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load inverter_flat
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cellname delete inverter -noprompt
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cellname rename inverter_flat inverter
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select top cell
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extract path /home/pedersen/misc/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC
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extract all
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ext2sim labels on
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ext2sim -p /home/pedersen/misc/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC
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extresist tolerance 1
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extresist all
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ext2spice short resistor
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ext2spice merge conservative
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ext2spice cthresh 0.02
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ext2spice extresist on
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ext2spice subcircuits top on
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ext2spice format ngspice
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ext2spice -p /home/pedersen/misc/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC -o /home/pedersen/misc/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC/inverter.pex.spice
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quit -noprompt
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