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# Layout and Physical Verification
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In this tutorial, we will guide you through the systematic process of laying out the bandgap reference circuit. This task is divided into two parts: the design of the two-stage OTA and the bandgap core, both of which were created in parts 1 and 2 of this series. The primary focus here is to transition the design from the schematic editor into KLayout for layout implementation, ensuring that pycells are correctly utilized in the layout process.
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### Extracting Pycells from the Netlist and Performing LVS
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Within part 3 of the tutorial, you will find the recommended setup for organizing your layout procedure. The `pycell_macro` folder contains the generator script we will use to create the layout. This script takes a netlist in the `.spice` format as input and processes it in batch mode. Here’s an example of how to use it for the two-stage OTA:
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### Exporting the Netlist Correctly
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Before starting the layout design, we must first export the netlist properly. To begin, launch the OTA design in **xschem** and navigate to the **Simulation** submenu. Within this menu, select the **LVS** option. Ensure that the **Use 'spiceprefix' attribute** checkbox is selected. Once this is done, click on **Netlist** to generate the corresponding simulation files.
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Navigate to the simulation folder, which is located in the same directory as your schematic file. You should see a `.spice` file with the same name as the schematic. Open this file in your preferred text editor. The content will look like the following:
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```
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** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sch
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**.subckt two_stage_OTA vdd iout v+ v- vout vss
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*.iopin v-
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*.iopin v+
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*.iopin vss
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*.iopin vdd
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*.iopin iout
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*.iopin vout
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XM4 net3 net1 vss vss sg13_lv_nmos w=720n l=9.75u ng=1 m=1
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XM3 net1 net1 vss vss sg13_lv_nmos w=720n l=9.75u ng=1 m=1
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XM1 net1 v- net2 vdd sg13_lv_pmos w=3.705u l=3.64u ng=1 m=1
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XM2 net3 v+ net2 vdd sg13_lv_pmos w=3.705u l=3.64u ng=1 m=1
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XM5 net2 iout vdd vdd sg13_lv_pmos w=5.3u l=1.95u ng=1 m=1
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XM7 vout iout vdd vdd sg13_lv_pmos w=75u l=2.08u ng=8 m=1
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XM6 vout net3 vss vss sg13_lv_nmos w=28.8u l=9.75u ng=4 m=1
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XM9 iout iout vdd vdd sg13_lv_pmos w=75u l=2.08u ng=8 m=1
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XC2 net3 vout cap_cmim w=22.295e-6 l=22.295e-6 m=1
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**.ends
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.end
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```
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### Understanding the Netlist
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A netlist is essentially a list of components and their connections used for simulations. Here's a breakdown of the main elements:
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- **Subcircuit Definition (`.subckt`)**: Defines the name of the circuit and its connections (e.g., `vdd`, `iout`, `v+`, etc.).
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- **Device Definitions (`XM`, `XC`)**: These lines represent components (e.g., transistors and capacitors) and their connections, along with key parameters like width, length, and model.
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- **Pins (`.iopin`)**: Specifies external connection points for the subcircuit.
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- **End Markers (`.ends`, `.end`)**: Marks the beginning and end of the subcircuit and netlist.
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We will also explore the use of CDL (Cadence Design Language) netlists for LVS later in the tutorial.
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### Creating the Device Gallery
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With the netlist verified, we can now proceed to create the GDS file containing our layout. To achieve this, we will utilize the generator script located in the `pycell_macro` folder. We want to run it in batch mode. Here’s the general form for executing the script:
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```
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klayout -n sg13g2 -zz -r generator.py -rd netlist=netlist.spice -rd output=macros/gallery.gds
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```
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For my setup, the generator and netlist files are located as follows:
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```
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/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_3_layout/pycell_macro/generator.py
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```
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```
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/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/simulations/two_stage_OTA.spice
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```
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The output file will be placed here:
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```
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/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/two_stage_OTA.gds
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```
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Thus, the final command to generate the GDS file will be:
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```
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klayout -n sg13g2 -zz -r /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_3_layout/pycell_macro/generator.py -rd netlist=/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/simulations/two_stage_OTA.spice -rd output=/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/two_stage_OTA.gds
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```
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After running this command, you can open the generated GDS file in KLayout using the following command:
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```
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klayout two_stage_OTA.gds -e
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```
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### Changing the Netlist Format for LVS
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As we move into the layout phase, performing LVS (Layout vs. Schematic) checks is crucial to ensure that the layout matches the schematic design. Preparing the netlist in the correct format is a key step in this process. For LVS, we require a `.cdl` format netlist. Here's how to prepare it:
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1. **Generate the Netlist in Xschem**:
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- Open your schematic in **Xschem**.
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- Navigate to the **Simulation** submenu and select the **LVS** option.
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- Deselect the **Use 'spiceprefix' attribute** checkbox.
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- Enable the option **LVS netlist: Top level is a .subckt**.
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- Click **Netlist** to generate the required file.
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2. **Rename the Extracted Netlist**:
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- Locate the generated `.spice` file in the **simulations** folder (it will have the same name as your schematic).
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- Rename the file extension from `.spice` to `.cdl`. For example, rename `two_stage_OTA.spice` to `two_stage_OTA.cdl`.
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- For safety, copy the renamed `.cdl` file to your **layout folder** to prevent accidental overwrites during future operations.
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3. **Inspect the CDL File**:
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- Open the `.cdl` file in a text editor to ensure its contents look correct. You should see something like this:
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```
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** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sch
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.subckt two_stage_OTA vdd iout v+ v- vout vss
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*.PININFO v-:B v+:B vss:B vdd:B iout:B vout:B
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M4 net3 net1 vss vss sg13_lv_nmos l=9.75u w=720n ng=1 m=1
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M3 net1 net1 vss vss sg13_lv_nmos l=9.75u w=720n ng=1 m=1
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M1 net1 v- net2 vdd sg13_lv_pmos l=3.64u w=3.705u ng=1 m=1
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M2 net3 v+ net2 vdd sg13_lv_pmos l=3.64u w=3.705u ng=1 m=1
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M5 net2 iout vdd vdd sg13_lv_pmos l=1.95u w=5.3u ng=1 m=1
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M7 vout iout vdd vdd sg13_lv_pmos l=2.08u w=75u ng=8 m=1
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M6 vout net3 vss vss sg13_lv_nmos l=9.75u w=28.8u ng=4 m=1
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M9 iout iout vdd vdd sg13_lv_pmos l=2.08u w=75u ng=8 m=1
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C2 net3 vout cap_cmim w=22.295e-6 l=22.295e-6 m=1
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.ends
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.end
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```
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- Note that the instance prefixes (e.g., `X`) have been removed, which is necessary for LVS.
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- **Update the Layout in KLayout**:
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- Open the layout in **KLayout**.
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- Navigate to the **Cells** menu and rename the top cell (e.g., `gallery`) to match the top cell name in your netlist. For instance, rename it to `two_stage_OTA` in this case.
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- **Run the LVS in KLayout**:
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- Open the **SG13G2 PDK** menu and select **SG13G2 LVS Options**.
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- In the small menu that appears, specify the path to your `.cdl` netlist file.
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- Click **OK** to save the settings.
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- Finally, navigate to the **LVS** option in the same menu to run the LVS check.
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At this point you should see a lot of uncorrected LVS issues.
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# Klayout video tutorial
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The linked video provides a walkthrough on designing the input pair of an OTA for a bandgap reference and demonstrates how to complete a layout using open-source tools. While this is not a comprehensive,
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end-to-end tutorial—such a deep dive would require far more time than is practical for a single video—it covers the essentials.
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You’ll learn how to navigate KLayout effectively and establish a solid layout workflow, laying the foundation for more advanced design tasks.
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