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create final layout

This commit is contained in:
PhillipRambo 2025-01-23 13:43:17 +01:00
parent e5e1c41028
commit 86422c7918
2 changed files with 988 additions and 0 deletions
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modules/module_1_bandgap_reference/part_3_layout/BGR_layout/final_bandgapreference/full_bandgap.gds Normal file
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modules/module_1_bandgap_reference/part_3_layout/BGR_layout/final_bandgapreference/schematic_mod/full_bandgap.sch Normal file
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v {xschem version=3.4.5 file_version=1.2
}
G {}
K {}
V {}
S {}
E {}
N 1500 -1405 1500 -1350 {
lab=#net1}
N 1645 -1535 1735 -1535 {
lab=vdd}
N 1575 -1485 1605 -1485 {
lab=#net1}
N 1500 -1405 1575 -1405 {
lab=#net1}
N 1500 -1455 1500 -1405 {
lab=#net1}
N 1575 -1485 1575 -1405 {
lab=#net1}
N 1540 -1485 1575 -1485 {
lab=#net1}
N 1645 -1405 1645 -1350 {
lab=#net2}
N 1500 -1265 1645 -1265 {
lab=vss}
N 1645 -1290 1645 -1265 {
lab=vss}
N 1540 -1320 1735 -1320 {
lab=v-}
N 1645 -1405 1695 -1405 {
lab=#net2}
N 1645 -1455 1645 -1405 {
lab=#net2}
N 1735 -1320 1735 -1205 {
lab=v-}
N 1735 -1375 1735 -1320 {
lab=v-}
N 1735 -1205 1810 -1205 {
lab=v-}
N 1440 -1485 1500 -1485 {
lab=bulk6}
N 1645 -1485 1690 -1485 {
lab=bulk6}
N 1645 -1535 1645 -1515 {
lab=vdd}
N 1500 -1535 1645 -1535 {
lab=vdd}
N 1500 -1535 1500 -1515 {
lab=vdd}
N 450 -245 470 -245 {
lab=#net3}
N 450 -305 450 -245 {
lab=#net3}
N 450 -305 510 -305 {
lab=#net3}
N 510 -145 675 -145 {
lab=vss}
N 210 -760 310 -760 {
lab=v-}
N 360 -985 360 -960 {
lab=vdd}
N 210 -960 360 -960 {
lab=vdd}
N 210 -860 210 -760 {
lab=v-}
N 510 -770 510 -760 {
lab=v+}
N 510 -760 510 -730 {
lab=v+}
N 510 -305 510 -275 {
lab=#net3}
N 360 -145 360 -115 {
lab=vss}
N 210 -145 360 -145 {
lab=vss}
N 250 -890 470 -890 {
lab=Vo1}
N 675 -920 675 -890 {
lab=Vo1}
N 510 -770 675 -770 {
lab=v+}
N 715 -860 715 -790 {
lab=VBG}
N 395 -760 510 -760 {
lab=v+}
N 510 -860 510 -770 {
lab=v+}
N 675 -770 675 -730 {
lab=v+}
N 510 -960 715 -960 {
lab=vdd}
N 880 -790 1110 -790 {
lab=VBG}
N 715 -960 715 -920 {
lab=vdd}
N 715 -890 805 -890 {
lab=bulk7}
N 510 -960 510 -920 {
lab=vdd}
N 360 -960 510 -960 {
lab=vdd}
N 510 -890 575 -890 {
lab=bulk7}
N 210 -960 210 -920 {
lab=vdd}
N 150 -890 210 -890 {
lab=bulk7}
N 210 -760 210 -275 {
lab=v-}
N 395 -760 395 -245 {
lab=v+}
N 880 -790 880 -735 {
lab=VBG}
N 715 -790 880 -790 {
lab=VBG}
N 1590 -1350 1645 -1350 {
lab=#net2}
N 1590 -1290 1645 -1290 {
lab=vss}
N 395 -1435 395 -1415 {
lab=dn2}
N 605 -1435 605 -1415 {
lab=dn2}
N 505 -1435 605 -1435 {
lab=dn2}
N 325 -1385 355 -1385 {
lab=v-}
N 645 -1385 675 -1385 {
lab=v+}
N 395 -1435 505 -1435 {
lab=dn2}
N 605 -1165 605 -1160 {
lab=dn4}
N 1450 -755 1450 -725 {
lab=vdd}
N 1490 -695 1490 -675 {
lab=dn4}
N 1255 -755 1255 -725 {
lab=vdd}
N 1295 -695 1295 -675 {
lab=dn3}
N 1450 -755 1490 -755 {
lab=vdd}
N 1255 -755 1295 -755 {
lab=vdd}
N 1450 -865 1450 -835 {
lab=vdd}
N 1490 -805 1490 -785 {
lab=dn2}
N 1255 -865 1255 -835 {
lab=vdd}
N 1295 -805 1295 -785 {
lab=dn2}
N 1450 -865 1490 -865 {
lab=vdd}
N 1255 -865 1295 -865 {
lab=vdd}
N 1300 -535 1300 -495 {
lab=vdd}
N 1295 -725 1400 -725 {
lab=bulk}
N 1295 -835 1400 -835 {
lab=bulk}
N 395 -1385 605 -1385 {
lab=bulk}
N 1490 -835 1595 -835 {
lab=bulk}
N 1490 -725 1595 -725 {
lab=bulk}
N 1300 -615 1300 -590 {
lab=bulk}
N 395 -1200 395 -1160 {
lab=dn3}
N 395 -1200 505 -1200 {
lab=dn3}
N 505 -1130 565 -1130 {
lab=dn3}
N 505 -1200 505 -1130 {
lab=dn3}
N 435 -1130 505 -1130 {
lab=dn3}
N 505 -1500 505 -1435 {
lab=dn2}
N 395 -1070 605 -1070 {
lab=vss}
N 1275 -370 1275 -335 {
lab=vss}
N 1275 -455 1275 -430 {
lab=sub!}
N 605 -1130 695 -1130 {
lab=sub!}
N 395 -1100 395 -1070 {
lab=vss}
N 300 -1130 395 -1130 {
lab=sub!}
N 605 -1100 605 -1070 {
lab=vss}
N 1415 -530 1415 -495 {
lab=vdd}
N 1415 -615 1415 -590 {
lab=bulk1}
N 505 -1575 505 -1560 {
lab=vdd}
N 505 -1530 585 -1530 {
lab=bulk1}
N 395 -1355 395 -1200 {
lab=dn3}
N 140 -1480 140 -1460 {
lab=iout}
N 140 -1480 190 -1480 {
lab=iout}
N 190 -1530 465 -1530 {
lab=iout}
N 140 -1500 140 -1480 {
lab=iout}
N 190 -1530 190 -1480 {
lab=iout}
N 180 -1530 190 -1530 {
lab=iout}
N 820 -1525 840 -1525 {
lab=iout}
N 880 -1375 920 -1375 {
lab=Vo1}
N 880 -1495 880 -1375 {
lab=Vo1}
N 780 -1165 840 -1165 {
lab=dn4}
N 780 -1225 780 -1165 {
lab=dn4}
N 880 -1225 880 -1195 {
lab=Vo1}
N 840 -1225 880 -1225 {
lab=Vo1}
N 880 -1375 880 -1225 {
lab=Vo1}
N 880 -1140 880 -1070 {
lab=vss}
N 880 -1165 960 -1165 {
lab=sub!}
N 880 -1575 880 -1555 {
lab=vdd}
N 75 -1530 140 -1530 {
lab=bulk4}
N 880 -1525 950 -1525 {
lab=bulk4}
N 1520 -620 1520 -590 {
lab=bulk4}
N 1520 -530 1520 -490 {
lab=vdd}
N 605 -1070 880 -1070 {
lab=vss}
N 605 -1165 780 -1165 {
lab=dn4}
N 605 -1355 605 -1165 {
lab=dn4}
N 505 -1580 505 -1575 {
lab=vdd}
N 505 -1575 880 -1575 {
lab=vdd}
N 140 -1575 505 -1575 {
lab=vdd}
N 140 -1575 140 -1560 {
lab=vdd}
N 1675 -620 1675 -590 {
lab=bulk6}
N 1675 -530 1675 -490 {
lab=vdd}
N 510 -215 510 -145 {
lab=vss}
N 360 -145 510 -145 {
lab=vss}
N 150 -245 210 -245 {
lab=sub!}
N 510 -245 565 -245 {
lab=sub!}
N 510 -350 510 -305 {
lab=#net3}
N 510 -425 510 -410 {
lab=#net4}
N 510 -505 510 -485 {
lab=#net5}
N 510 -585 510 -565 {
lab=#net6}
N 510 -670 510 -645 {
lab=#net7}
N 675 -350 675 -145 {
lab=vss}
N 675 -425 675 -410 {
lab=#net8}
N 675 -500 675 -485 {
lab=#net9}
N 675 -585 675 -560 {
lab=#net10}
N 675 -670 675 -645 {
lab=#net11}
N 880 -240 880 -145 {
lab=vss}
N 675 -145 880 -145 {
lab=vss}
N 880 -675 880 -660 {
lab=#net12}
N 880 -600 880 -590 {
lab=#net13}
N 880 -530 880 -520 {
lab=#net14}
N 880 -460 880 -445 {
lab=#net15}
N 880 -385 880 -375 {
lab=#net16}
N 880 -315 880 -300 {
lab=#net17}
N 210 -215 210 -145 {
lab=vss}
N 250 -245 395 -245 {
lab=v+}
N 1500 -1290 1500 -1265 {
lab=vss}
N 1435 -1320 1500 -1320 {
lab=sub!}
N 1735 -1535 1735 -1435 {
lab=vdd}
N 1735 -1405 1800 -1405 {
lab=bulk5}
N 1600 -620 1600 -590 {
lab=bulk5}
N 1600 -530 1600 -490 {
lab=vdd}
N 1755 -620 1755 -590 {
lab=bulk7}
N 1755 -530 1755 -490 {
lab=vdd}
N 1690 -855 1690 -785 {
lab=vdd}
N 1690 -855 1730 -855 {
lab=vdd}
N 1730 -855 1730 -815 {
lab=vdd}
N 1690 -785 1730 -785 {
lab=vdd}
N 1825 -855 1825 -785 {
lab=vdd}
N 1825 -855 1865 -855 {
lab=vdd}
N 1865 -855 1865 -815 {
lab=vdd}
N 1825 -785 1865 -785 {
lab=vdd}
N 1695 -770 1695 -700 {
lab=vdd}
N 1695 -770 1735 -770 {
lab=vdd}
N 1735 -770 1735 -730 {
lab=vdd}
N 1695 -700 1735 -700 {
lab=vdd}
N 1830 -770 1830 -700 {
lab=vdd}
N 1830 -770 1870 -770 {
lab=vdd}
N 1870 -770 1870 -730 {
lab=vdd}
N 1830 -700 1870 -700 {
lab=vdd}
N 1950 -855 1950 -785 {
lab=vdd}
N 1950 -855 1990 -855 {
lab=vdd}
N 1990 -855 1990 -815 {
lab=vdd}
N 1950 -785 1990 -785 {
lab=vdd}
N 1950 -775 1950 -705 {
lab=vdd}
N 1950 -775 1990 -775 {
lab=vdd}
N 1990 -775 1990 -735 {
lab=vdd}
N 1950 -705 1990 -705 {
lab=vdd}
N 2075 -775 2075 -705 {
lab=vdd}
N 2075 -775 2115 -775 {
lab=vdd}
N 2115 -775 2115 -735 {
lab=vdd}
N 2075 -705 2115 -705 {
lab=vdd}
N 2075 -855 2075 -785 {
lab=vdd}
N 2075 -855 2115 -855 {
lab=vdd}
N 2115 -855 2115 -815 {
lab=vdd}
N 2075 -785 2115 -785 {
lab=vdd}
N 2200 -775 2200 -705 {
lab=vdd}
N 2200 -775 2240 -775 {
lab=vdd}
N 2240 -775 2240 -735 {
lab=vdd}
N 2200 -705 2240 -705 {
lab=vdd}
N 2200 -855 2200 -785 {
lab=vdd}
N 2200 -855 2240 -855 {
lab=vdd}
N 2240 -855 2240 -815 {
lab=vdd}
N 2200 -785 2240 -785 {
lab=vdd}
N 1355 -365 1355 -330 {
lab=vss}
N 1355 -450 1355 -425 {
lab=sub!}
N 1430 -365 1430 -330 {
lab=vss}
N 1430 -450 1430 -425 {
lab=sub!}
N 1510 -365 1510 -330 {
lab=vss}
N 1510 -450 1510 -425 {
lab=sub!}
N 1590 -365 1590 -330 {
lab=vss}
N 1590 -450 1590 -425 {
lab=sub!}
N 1670 -360 1670 -325 {
lab=vss}
N 1670 -445 1670 -420 {
lab=sub!}
C {devices/code_shown.sym} 1110 -215 0 0 {name=MODEL only_toplevel=true
format="tcleval( @value )"
value="
.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ
.lib $::SG13G2_MODELS/cornerRES.lib res_typ
.lib cornerMOSlv.lib mos_tt
"}
C {sg13g2_pr/sg13_lv_nmos.sym} 1520 -1320 2 0 {name=M8
l=10u
w=150n
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 1520 -1485 0 1 {name=M6
l=1u
w=1u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 1625 -1485 0 0 {name=M7
l=1u
w=1u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 1715 -1405 0 0 {name=M9
l=4u
w=200n
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 1735 -1535 0 1 {name=p5 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 1690 -1485 0 1 {name=p4 sig_type=std_logic lab=bulk6}
C {lab_pin.sym} 1440 -1485 0 0 {name=p17 sig_type=std_logic lab=bulk6}
C {sg13g2_pr/sg13_lv_nmos.sym} 230 -245 2 0 {name=M1
l=5u
w=7.14u
ng=4
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 490 -245 2 1 {name=M2
l=5u
w=21u
ng=8
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 230 -890 0 1 {name=M3
l=5u
w=15u
ng=8
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 490 -890 0 0 {name=M4
l=5u
w=15u
ng=8
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 360 -985 0 1 {name=p2 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 310 -760 3 0 {name=p3 sig_type=std_logic lab=v-}
C {lab_pin.sym} 395 -760 0 0 {name=p8 sig_type=std_logic lab=v+}
C {lab_pin.sym} 365 -890 1 1 {name=p9 sig_type=std_logic lab=Vo1}
C {sg13g2_pr/sg13_lv_pmos.sym} 695 -890 0 0 {name=M5
l=5u
w=16u
ng=8
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {opin.sym} 1110 -790 0 0 {name=p11 lab=VBG}
C {lab_pin.sym} 675 -920 2 1 {name=p12 sig_type=std_logic lab=Vo1}
C {lab_pin.sym} 150 -890 0 0 {name=p13 sig_type=std_logic lab=bulk7}
C {lab_pin.sym} 575 -890 0 1 {name=p14 sig_type=std_logic lab=bulk7}
C {lab_pin.sym} 805 -890 0 1 {name=p15 sig_type=std_logic lab=bulk7}
C {sg13g2_pr/rppd.sym} 880 -705 0 0 {name=R2
w=0.710e-6
l=38.65e-6
model=rppd
spiceprefix=X
b=0
m=1
}
C {sg13g2_pr/cap_cmim.sym} 1590 -1320 0 0 {name=C1
model=cap_cmim
w=18.195e-6
l=18.195e-6
m=1
spiceprefix=X}
C {lab_pin.sym} 360 -115 0 0 {name=p6 sig_type=std_logic lab=vss}
C {sg13g2_pr/sg13_lv_pmos.sym} 375 -1385 0 0 {name=M10
l=3.7u
w=3.64u
ng=1
m=2
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 625 -1385 0 1 {name=M11
l=3.7u
w=3.64u
ng=1
m=2
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 1470 -725 0 0 {name=M12
l=3.7u
w=3.64u
ng=1
m=2
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 1450 -755 0 0 {name=p20 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 1275 -725 0 0 {name=M13
l=3.7u
w=3.64u
ng=1
m=2
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 1255 -755 0 0 {name=p21 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 1295 -675 0 0 {name=p43 sig_type=std_logic lab=dn3}
C {lab_pin.sym} 1490 -675 0 0 {name=p22 sig_type=std_logic lab=dn4}
C {sg13g2_pr/sg13_lv_pmos.sym} 1470 -835 0 0 {name=M15
l=3.7u
w=3.64u
ng=1
m=2
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 1450 -865 0 0 {name=p49 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 1275 -835 0 0 {name=M16
l=3.7u
w=3.64u
ng=1
m=2
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 1255 -865 0 0 {name=p50 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 1295 -785 0 0 {name=p53 sig_type=std_logic lab=dn2}
C {lab_pin.sym} 1490 -785 0 0 {name=p54 sig_type=std_logic lab=dn2}
C {sg13g2_pr/ntap1.sym} 1300 -560 0 0 {name=R4
model=ntap1
spiceprefix=X
w=13e-6
l=34e-6
}
C {lab_pin.sym} 1300 -495 0 0 {name=p23 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 1595 -835 0 1 {name=p24 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 1400 -835 0 1 {name=p25 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 1400 -725 0 1 {name=p26 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 1595 -725 0 1 {name=p27 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 1300 -615 0 1 {name=p28 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 505 -1385 1 1 {name=p29 sig_type=std_logic lab=bulk}
C {sg13g2_pr/sg13_lv_pmos.sym} 485 -1530 0 0 {name=M14
l=1.95u
w=5.3u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {iopin.sym} 505 -1070 1 1 {name=p30 lab=vss}
C {iopin.sym} 505 -1580 1 1 {name=p31 lab=vdd}
C {lab_pin.sym} 695 -1130 0 1 {name=p32 sig_type=std_logic lab=sub!}
C {sg13g2_pr/ptap1.sym} 1275 -400 0 0 {name=R5
model=ptap1
spiceprefix=X
w=10e-6
l=1.0e-6
}
C {lab_pin.sym} 1275 -335 0 0 {name=p33 sig_type=std_logic lab=vss}
C {lab_pin.sym} 1275 -455 0 1 {name=p34 sig_type=std_logic lab=sub!}
C {lab_pin.sym} 1415 -495 0 0 {name=p35 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 1415 -615 0 1 {name=p36 sig_type=std_logic lab=bulk1}
C {sg13g2_pr/ntap1.sym} 1415 -560 0 0 {name=R6
model=ntap1
spiceprefix=X
w=0.78e-6
l=0.78e-6
}
C {lab_pin.sym} 585 -1530 0 1 {name=p37 sig_type=std_logic lab=bulk1}
C {sg13g2_pr/sg13_lv_nmos.sym} 415 -1130 2 0 {name=M17
l=9.75u
w=720n
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 585 -1130 2 1 {name=M18
l=9.75u
w=720n
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {lab_pin.sym} 305 -1130 0 0 {name=p38 sig_type=std_logic lab=sub!}
C {sg13g2_pr/sg13_lv_pmos.sym} 860 -1525 0 0 {name=M19
l=2.08u
w=75u
ng=8
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 860 -1165 2 1 {name=M20
l=9.75u
w=28.8u
ng=4
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {iopin.sym} 140 -1460 0 1 {name=p39 lab=iout}
C {lab_pin.sym} 820 -1525 0 0 {name=p41 sig_type=std_logic lab=iout}
C {sg13g2_pr/sg13_lv_pmos.sym} 160 -1530 0 1 {name=M21
l=2.08u
w=75u
ng=8
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/cap_cmim.sym} 810 -1225 3 0 {name=C2
model=cap_cmim
w=22.295e-6
l=22.295e-6
m=1
spiceprefix=X}
C {lab_pin.sym} 960 -1165 0 1 {name=p45 sig_type=std_logic lab=sub!}
C {lab_pin.sym} 75 -1530 0 0 {name=p46 sig_type=std_logic lab=bulk4}
C {lab_pin.sym} 950 -1525 2 0 {name=p47 sig_type=std_logic lab=bulk4}
C {lab_pin.sym} 1520 -620 0 1 {name=p48 sig_type=std_logic lab=bulk4}
C {lab_pin.sym} 1520 -490 0 0 {name=p51 sig_type=std_logic lab=vdd}
C {sg13g2_pr/ntap1.sym} 1520 -560 0 0 {name=R8
model=ntap1
spiceprefix=X
R=262.847.0
Imax=0.3e-6
}
C {lab_pin.sym} 395 -1270 0 0 {name=p52 sig_type=std_logic lab=dn3}
C {lab_pin.sym} 605 -1275 0 0 {name=p55 sig_type=std_logic lab=dn4}
C {lab_pin.sym} 505 -1465 0 0 {name=p56 sig_type=std_logic lab=dn2}
C {lab_pin.sym} 920 -1375 1 1 {name=p10 sig_type=std_logic lab=Vo1}
C {lab_pin.sym} 325 -1385 3 0 {name=p18 sig_type=std_logic lab=v-}
C {lab_pin.sym} 675 -1385 0 1 {name=p19 sig_type=std_logic lab=v+}
C {lab_pin.sym} 1810 -1205 3 0 {name=p1 sig_type=std_logic lab=v-}
C {lab_pin.sym} 1675 -620 0 1 {name=p7 sig_type=std_logic lab=bulk6}
C {lab_pin.sym} 1675 -490 0 0 {name=p16 sig_type=std_logic lab=vdd}
C {sg13g2_pr/ntap1.sym} 1675 -560 0 0 {name=R9
model=ntap1
spiceprefix=X
R=8.463
Imax=0.3e-6
}
C {lab_pin.sym} 150 -245 0 0 {name=p40 sig_type=std_logic lab=sub!}
C {lab_pin.sym} 565 -245 0 1 {name=p57 sig_type=std_logic lab=sub!}
C {sg13g2_pr/rppd.sym} 510 -700 0 0 {name=R12
w=0.5e-6
l=38.65e-6
model=rppd
spiceprefix=X
b=0
m=1
}
C {sg13g2_pr/rppd.sym} 510 -615 0 0 {name=R3
w=0.5e-6
l=38.65e-6
model=rppd
spiceprefix=X
b=0
m=1
}
C {sg13g2_pr/rppd.sym} 510 -535 0 0 {name=R13
w=0.5e-6
l=38.65e-6
model=rppd
spiceprefix=X
b=0
m=1
}
C {sg13g2_pr/rppd.sym} 510 -455 0 0 {name=R14
w=0.5e-6
l=38.65e-6
model=rppd
spiceprefix=X
b=0
m=1
}
C {sg13g2_pr/rppd.sym} 510 -380 0 0 {name=R15
w=0.5e-6
l=38.65e-6
model=rppd
spiceprefix=X
b=0
m=1
}
C {sg13g2_pr/rppd.sym} 675 -700 0 0 {name=R1
w=0.5e-6
l=38.65e-6
model=rppd
spiceprefix=X
b=0
m=1
}
C {sg13g2_pr/rppd.sym} 675 -615 0 0 {name=R16
w=0.5e-6
l=38.65e-6
model=rppd
spiceprefix=X
b=0
m=1
}
C {sg13g2_pr/rppd.sym} 675 -530 0 0 {name=R17
w=0.5e-6
l=38.65e-6
model=rppd
spiceprefix=X
b=0
m=1
}
C {sg13g2_pr/rppd.sym} 675 -455 0 0 {name=R18
w=0.5e-6
l=38.65e-6
model=rppd
spiceprefix=X
b=0
m=1
}
C {sg13g2_pr/rppd.sym} 675 -380 0 0 {name=R19
w=3e-6
l=38.65e-6
model=rppd
spiceprefix=X
b=0
m=1
}
C {sg13g2_pr/rppd.sym} 880 -630 0 0 {name=R20
w=0.710e-6
l=38.65e-6
model=rppd
spiceprefix=X
b=0
m=1
}
C {sg13g2_pr/rppd.sym} 880 -560 0 0 {name=R21
w=0.710e-6
l=38.65e-6
model=rppd
spiceprefix=X
b=0
m=1
}
C {sg13g2_pr/rppd.sym} 880 -490 0 0 {name=R22
w=0.710e-6
l=38.65e-6
model=rppd
spiceprefix=X
b=0
m=1
}
C {sg13g2_pr/rppd.sym} 880 -415 0 0 {name=R23
w=0.710e-6
l=38.65e-6
model=rppd
spiceprefix=X
b=0
m=1
}
C {sg13g2_pr/rppd.sym} 880 -345 0 0 {name=R24
w=0.710e-6
l=38.65e-6
model=rppd
spiceprefix=X
b=0
m=1
}
C {sg13g2_pr/rppd.sym} 880 -270 0 0 {name=R25
w=0.710e-6
l=38.65e-6
model=rppd
spiceprefix=X
b=0
m=1
}
C {lab_pin.sym} 1520 -1265 3 0 {name=p62 sig_type=std_logic lab=vss}
C {lab_pin.sym} 1435 -1320 0 0 {name=p63 sig_type=std_logic lab=sub!}
C {lab_pin.sym} 1800 -1405 0 1 {name=p64 sig_type=std_logic lab=bulk5}
C {lab_pin.sym} 1600 -620 0 1 {name=p65 sig_type=std_logic lab=bulk5}
C {lab_pin.sym} 1600 -490 0 0 {name=p66 sig_type=std_logic lab=vdd}
C {sg13g2_pr/ntap1.sym} 1600 -560 0 0 {name=R26
model=ntap1
spiceprefix=X
R=8.463
Imax=0.3e-6
}
C {lab_pin.sym} 1755 -620 0 1 {name=p67 sig_type=std_logic lab=bulk7}
C {lab_pin.sym} 1755 -490 0 0 {name=p68 sig_type=std_logic lab=vdd}
C {sg13g2_pr/ntap1.sym} 1755 -560 0 0 {name=R27
model=ntap1
spiceprefix=X
R=8.463
Imax=0.3e-6
}
C {sg13g2_pr/sg13_lv_pmos.sym} 1710 -815 0 0 {name=M22
l=5u
w=10u
ng=4
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 1690 -855 0 0 {name=p69 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 1845 -815 0 0 {name=M23
l=5u
w=10u
ng=4
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 1825 -855 0 0 {name=p70 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 1715 -730 0 0 {name=M24
l=5u
w=10u
ng=4
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 1695 -770 0 0 {name=p71 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 1850 -730 0 0 {name=M25
l=5u
w=10u
ng=4
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 1830 -770 0 0 {name=p72 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 1970 -815 0 0 {name=M26
l=5u
w=10u
ng=4
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 1950 -855 0 0 {name=p73 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 1970 -735 0 0 {name=M27
l=4u
w=5u
ng=2
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 1950 -775 0 0 {name=p74 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 2095 -735 0 0 {name=M28
l=4u
w=5u
ng=2
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 2075 -775 0 0 {name=p75 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 2095 -815 0 0 {name=M29
l=4u
w=5u
ng=2
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 2075 -855 0 0 {name=p76 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 2220 -735 0 0 {name=M30
l=4u
w=5u
ng=2
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 2200 -775 0 0 {name=p77 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 2220 -815 0 0 {name=M31
l=4u
w=5u
ng=2
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 2200 -855 0 0 {name=p78 sig_type=std_logic lab=vdd}
C {sg13g2_pr/ptap1.sym} 1355 -395 0 0 {name=R7
model=ptap1
spiceprefix=X
w=10e-6
l=1.0e-6
}
C {lab_pin.sym} 1355 -330 0 0 {name=p42 sig_type=std_logic lab=vss}
C {lab_pin.sym} 1355 -450 0 1 {name=p44 sig_type=std_logic lab=sub!}
C {sg13g2_pr/ptap1.sym} 1430 -395 0 0 {name=R10
model=ptap1
spiceprefix=X
w=10e-6
l=1.0e-6
}
C {lab_pin.sym} 1430 -330 0 0 {name=p58 sig_type=std_logic lab=vss}
C {lab_pin.sym} 1430 -450 0 1 {name=p59 sig_type=std_logic lab=sub!}
C {sg13g2_pr/ptap1.sym} 1510 -395 0 0 {name=R11
model=ptap1
spiceprefix=X
w=10e-6
l=1.0e-6
}
C {lab_pin.sym} 1510 -330 0 0 {name=p60 sig_type=std_logic lab=vss}
C {lab_pin.sym} 1510 -450 0 1 {name=p61 sig_type=std_logic lab=sub!}
C {sg13g2_pr/ptap1.sym} 1590 -395 0 0 {name=R28
model=ptap1
spiceprefix=X
w=10e-6
l=1.0e-6
}
C {lab_pin.sym} 1590 -330 0 0 {name=p79 sig_type=std_logic lab=vss}
C {lab_pin.sym} 1590 -450 0 1 {name=p80 sig_type=std_logic lab=sub!}
C {sg13g2_pr/ptap1.sym} 1670 -390 0 0 {name=R29
model=ptap1
spiceprefix=X
w=10e-6
l=1.0e-6
}
C {lab_pin.sym} 1670 -325 0 0 {name=p81 sig_type=std_logic lab=vss}
C {lab_pin.sym} 1670 -445 0 1 {name=p82 sig_type=std_logic lab=sub!}