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push new monte carlo

This commit is contained in:
PhillipRambo 2026-02-02 14:11:05 +01:00
parent 16fb57ae58
commit 8677bec494
2 changed files with 0 additions and 26 deletions
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12
modules/module_1_bandgap_reference/part_1_OTA/testbenches/simulations/ota_simple
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** OTA_SIMPLE flat netlist
*.PININFO V-:B V+:B VSS:B VDD:B IOUT:B VOUT:B
M4 NET3 NET1 VSS VSS SG13_LV_NMOS L=9.75U W=720N NG=1 M=1
M3 NET1 NET1 VSS VSS SG13_LV_NMOS L=9.75U W=720N NG=1 M=1
M1 NET1 V- NET2 VDD SG13_LV_PMOS L=3.64U W=7.41U NG=1 M=1
M2 NET3 V+ NET2 VDD SG13_LV_PMOS L=3.64U W=7.41U NG=1 M=1
M5 NET2 IOUT VDD VDD SG13_LV_PMOS L=1.95U W=5.3U NG=1 M=1
M7 VOUT IOUT VDD VDD SG13_LV_PMOS L=2.08U W=75U NG=8 M=1
M6 VOUT NET3 VSS VSS SG13_LV_NMOS L=9.75U W=28.8U NG=4 M=1
M9 IOUT IOUT VDD VDD SG13_LV_PMOS L=2.08U W=75U NG=8 M=1
C2 NET3 VOUT CAP_CMIM W=22.295E-6 L=22.295E-6 M=1
.end

14
modules/module_1_bandgap_reference/part_1_OTA/testbenches/simulations/stage_OTA.cdl
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** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sch
.subckt two_stage_OTA vdd iout v+ v- vout vss
*.PININFO v-:B v+:B vss:B vdd:B iout:B vout:B
M4 net3 net1 vss vss sg13_lv_nmos l=9.75u w=720n ng=1 m=1
M3 net1 net1 vss vss sg13_lv_nmos l=9.75u w=720n ng=1 m=1
M1 net1 v- net2 vdd sg13_lv_pmos l=3.64u w=3.705u ng=1 m=1
M2 net3 v+ net2 vdd sg13_lv_pmos l=3.64u w=3.705u ng=1 m=1
M5 net2 iout vdd vdd sg13_lv_pmos l=1.95u w=5.3u ng=1 m=1
M7 vout iout vdd vdd sg13_lv_pmos l=2.08u w=75u ng=8 m=1
M6 vout net3 vss vss sg13_lv_nmos l=9.75u w=28.8u ng=4 m=1
M9 iout iout vdd vdd sg13_lv_pmos l=2.08u w=75u ng=8 m=1
C2 net3 vout cap_cmim w=22.295e-6 l=22.295e-6 m=1
.ends
.end