From 8677bec494c69f151a18a8b18eaeb5af49cbe9ca Mon Sep 17 00:00:00 2001 From: PhillipRambo Date: Mon, 2 Feb 2026 14:11:05 +0100 Subject: [PATCH] push new monte carlo --- .../part_1_OTA/testbenches/simulations/ota_simple | 12 ------------ .../testbenches/simulations/stage_OTA.cdl | 14 -------------- 2 files changed, 26 deletions(-) delete mode 100644 modules/module_1_bandgap_reference/part_1_OTA/testbenches/simulations/ota_simple delete mode 100644 modules/module_1_bandgap_reference/part_1_OTA/testbenches/simulations/stage_OTA.cdl diff --git a/modules/module_1_bandgap_reference/part_1_OTA/testbenches/simulations/ota_simple b/modules/module_1_bandgap_reference/part_1_OTA/testbenches/simulations/ota_simple deleted file mode 100644 index 2e685e4f..00000000 --- a/modules/module_1_bandgap_reference/part_1_OTA/testbenches/simulations/ota_simple +++ /dev/null @@ -1,12 +0,0 @@ -** OTA_SIMPLE flat netlist -*.PININFO V-:B V+:B VSS:B VDD:B IOUT:B VOUT:B -M4 NET3 NET1 VSS VSS SG13_LV_NMOS L=9.75U W=720N NG=1 M=1 -M3 NET1 NET1 VSS VSS SG13_LV_NMOS L=9.75U W=720N NG=1 M=1 -M1 NET1 V- NET2 VDD SG13_LV_PMOS L=3.64U W=7.41U NG=1 M=1 -M2 NET3 V+ NET2 VDD SG13_LV_PMOS L=3.64U W=7.41U NG=1 M=1 -M5 NET2 IOUT VDD VDD SG13_LV_PMOS L=1.95U W=5.3U NG=1 M=1 -M7 VOUT IOUT VDD VDD SG13_LV_PMOS L=2.08U W=75U NG=8 M=1 -M6 VOUT NET3 VSS VSS SG13_LV_NMOS L=9.75U W=28.8U NG=4 M=1 -M9 IOUT IOUT VDD VDD SG13_LV_PMOS L=2.08U W=75U NG=8 M=1 -C2 NET3 VOUT CAP_CMIM W=22.295E-6 L=22.295E-6 M=1 -.end diff --git a/modules/module_1_bandgap_reference/part_1_OTA/testbenches/simulations/stage_OTA.cdl b/modules/module_1_bandgap_reference/part_1_OTA/testbenches/simulations/stage_OTA.cdl deleted file mode 100644 index 3ef56606..00000000 --- a/modules/module_1_bandgap_reference/part_1_OTA/testbenches/simulations/stage_OTA.cdl +++ /dev/null @@ -1,14 +0,0 @@ -** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sch -.subckt two_stage_OTA vdd iout v+ v- vout vss -*.PININFO v-:B v+:B vss:B vdd:B iout:B vout:B -M4 net3 net1 vss vss sg13_lv_nmos l=9.75u w=720n ng=1 m=1 -M3 net1 net1 vss vss sg13_lv_nmos l=9.75u w=720n ng=1 m=1 -M1 net1 v- net2 vdd sg13_lv_pmos l=3.64u w=3.705u ng=1 m=1 -M2 net3 v+ net2 vdd sg13_lv_pmos l=3.64u w=3.705u ng=1 m=1 -M5 net2 iout vdd vdd sg13_lv_pmos l=1.95u w=5.3u ng=1 m=1 -M7 vout iout vdd vdd sg13_lv_pmos l=2.08u w=75u ng=8 m=1 -M6 vout net3 vss vss sg13_lv_nmos l=9.75u w=28.8u ng=4 m=1 -M9 iout iout vdd vdd sg13_lv_pmos l=2.08u w=75u ng=8 m=1 -C2 net3 vout cap_cmim w=22.295e-6 l=22.295e-6 m=1 -.ends -.end