push new slider folders

modules/module_0_foundations/PEX_Demo/invert_test.sch

@@ -0,0 +1,84 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+B 2 710 -550 1510 -150 {flags=graph
+y1=0
+y2=0.01
+ypos1=0
+ypos2=2
+divy=5
+subdivy=1
+unity=1
+x1=0
+x2=2e-06
+divx=5
+subdivx=1
+xlabmag=1.0
+ylabmag=1.0
+node=vout
+color=4
+dataset=-1
+unitx=1
+logx=0
+logy=0
+}
+N 150 -170 150 -140 {lab=Vin}
+N 70 -170 70 -140 {lab=Vdd}
+N 70 -80 70 -60 {lab=GND}
+N 110 -60 150 -60 {lab=GND}
+N 150 -80 150 -60 {lab=GND}
+N 110 -60 110 -50 {lab=GND}
+N 70 -60 110 -60 {lab=GND}
+N 320 -410 320 -380 {lab=Vdd}
+N 320 -210 320 -190 {lab=GND}
+N 220 -300 240 -300 {lab=Vin}
+N 520 -300 540 -300 {lab=Vout}
+C {vsource.sym} 150 -110 0 0 {name=V1 value="PULSE(0 1.2 0.5u 10n 10n 1u 2u 1)" savecurrent=false}
+C {vsource.sym} 70 -110 0 0 {name=V2 value=1.2 savecurrent=false}
+C {gnd.sym} 110 -50 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 150 -170 0 0 {name=p1 sig_type=std_logic lab=Vin}
+C {lab_pin.sym} 70 -170 0 0 {name=p3 sig_type=std_logic lab=Vdd}
+C {code_shown.sym} 40 -540 0 0 {name=NGSPICE
+only_toplevel=true
+value="
+.control
+save all
+tran 50n 2u 
+write test_inverter.raw
+.endc
+" }
+C {launcher.sym} 770 -120 0 0 {name=h5
+descr="load waves" 
+tclcommand="xschem raw_read $netlist_dir/test_inverter.raw tran"
+}
+C {lab_pin.sym} 220 -300 0 0 {name=p2 sig_type=std_logic lab=Vin}
+C {gnd.sym} 320 -190 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 320 -410 0 0 {name=p4 sig_type=std_logic lab=Vdd}
+C {lab_pin.sym} 540 -300 0 1 {name=p5 sig_type=std_logic lab=Vout}
+C {inverter_test.sym} 390 -300 0 0 {name=x2
+schematic=inverter
+spice_sym_def="
+* NGSPICE file created from inverter.ext - technology: ihp-sg13g2
+
+.subckt inverter Vout Vin Gnd Vdd
+X0 Vout Vin Vdd Vdd sg13_lv_pmos ad=0.68p pd=4.68u as=0.68p ps=4.68u w=2u l=0.45u
+X1 Vout Vin Gnd Gnd sg13_lv_nmos ad=0.34p pd=2.68u as=0.34p ps=2.68u w=1u l=0.45u
+C0 Vout Vdd 0.13155f
+C1 Vout Vin 0.10077f
+C2 Vin Vdd 0.14482f
+C3 Vout Gnd 0.39245f
+C4 Vin Gnd 0.64666f
+C5 Vdd Gnd 0.15308f
+.ends
+"
+}
+C {devices/code_shown.sym} 300 -540 0 0 {name=MODEL only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib cornerMOSlv.lib mos_tt
+.lib cornerRES.lib res_typ
+
+"}

modules/module_0_foundations/PEX_Demo/inverter_test.sym

@@ -0,0 +1,26 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"}
+V {}
+S {}
+E {}
+L 7 -70 -80 -70 -60 {}
+L 7 -150 0 -130 0 {}
+L 7 110 0 130 0 {}
+L 7 -70 70 -70 90 {}
+B 5 -72.5 -82.5 -67.5 -77.5 {name=Vdd dir=inout}
+B 5 -152.5 -2.5 -147.5 2.5 {name=Vin dir=inout}
+B 5 127.5 -2.5 132.5 2.5 {name=Vout dir=inout}
+B 5 -72.5 87.5 -67.5 92.5 {name=Gnd dir=inout}
+A 4 105 0 7.071067811865476 135 360 {}
+P 4 5 100 0 -130 -80 -130 90 100 0 100 0 {}
+T {@symname
+
+} -84 -6 0 0 0.3 0.3 {}
+T {@name} -45 -32 0 0 0.2 0.2 {}
+T {Vdd} -74 -55 3 1 0.2 0.2 {}
+T {Vin} -125 -4 0 0 0.2 0.2 {}
+T {Vout} 80 -9 0 1 0.2 0.2 {}
+T {Gnd} -66 65 1 1 0.2 0.2 {}

modules/module_0_foundations/PEX_Demo/layout/inverter_extracted.cir

@@ -0,0 +1,10 @@
+* Extracted by KLayout with SG13G2 LVS runset on : 07/07/2025 16:12
+
+.SUBCKT inverter Gnd Vout Vin Vdd
+M$1 Gnd Vin Vout \$1 sg13_lv_nmos L=0.45u W=1u AS=0.34p AD=0.34p PS=2.68u
++ PD=2.68u
+M$2 Vdd Vin Vout \$2 sg13_lv_pmos L=0.45u W=2u AS=0.68p AD=0.68p PS=4.68u
++ PD=4.68u
+R$3 \$2 Vdd ntap1 A=0.6084p P=3.12u
+R$4 \$1 Gnd ptap1 A=0.6084p P=3.12u
+.ENDS inverter

modules/module_0_foundations/PEX_Demo/pex/kpex.sh

@@ -0,0 +1,32 @@
+#!/bin/bash
+set -e
+
+# Hardcoded paths (except PDK stuff)
+
+LAYOUT_PATH="../layout/inverter.gds"
+SCHEMATIC="../simulations/inverter.spice"
+
+
+PDK_NAME="ihp_sg13g2"
+MAGICRC="$PDK_ROOT/$PDK/libs.tech/magic/ihp-sg13g2.magicrc" # The magicrc file for your PDK, used during extraction
+
+
+# Run parasitic extraction with kpex
+kpex \
+  --pdk "$PDK_NAME" \
+  --magic \
+  --schematic "$SCHEMATIC" \
+  --gds "$LAYOUT_PATH" \
+  --magicrc "$MAGICRC" \
+  --magic_mode CC \
+  --magic_cthresh 0.02 \
+  --magic_rthresh 50 \
+  --magic_short resistor \
+  --magic_merge conservative \
+  --out_dir ./pex_output
+  
+  
+  
+  
+  
+

modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_CC/inverter.ext

@@ -0,0 +1,23 @@
+timestamp 0
+version 8.3
+tech ihp-sg13g2
+style ngspice()
+scale 1000 1 0.5
+resistclasses 3000000 67000 110 88 88 88 88 18 11
+parameters sg13_lv_nmos l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sg13_lv_pmos l=l w=w a1=as p1=ps a2=ad p2=pd
+port "Vout" 2 266 -211 298 -173 m1
+port "Vin" 3 95 -213 127 -175 m1
+port "Vdd" 5 -205 318 -173 356 m1
+port "Gnd" 4 20 -732 52 -694 m1
+node "ptap1_0.sub!" 0 0 28 -796 isosub 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vout" 1 392.446 266 -211 m1 0 0 0 0 91916 2354 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vin" 0 646.659 95 -213 m1 0 0 0 0 13590 482 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vdd" 1 153.076 -205 318 m1 0 0 0 0 42800 1364 0 0 0 0 0 0 0 0 0 0 0 0
+equiv "Vdd" "ntap1_0.well"
+substrate "Gnd" 0 0 20 -732 m1 0 0 0 0 21536 1036 0 0 0 0 0 0 0 0 0 0 0 0
+cap "Vout" "Vdd" 131.55
+cap "Vin" "Vdd" 144.819
+cap "Vout" "Vin" 100.772
+device msubckt sg13_lv_nmos 67 -562 68 -561 l=90 w=200 "Gnd" "Vin" 180 0 "Gnd" 200 13600,536 "Vout" 200 13600,536
+device msubckt sg13_lv_pmos 67 9 68 10 l=90 w=400 "Vdd" "Vin" 180 0 "Vdd" 400 27200,936 "Vout" 400 27200,936

modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_CC/inverter_MAGIC_CC_Script.tcl

@@ -0,0 +1,20 @@
+# Generated by kpex 0.3.6
+crashbackups stop
+drc off
+gds read /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/PEX_Demo/layout/inverter.gds
+load inverter
+select top cell
+flatten inverter_flat
+load inverter_flat
+cellname delete inverter -noprompt
+cellname rename inverter_flat inverter
+select top cell
+extract path /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_CC
+extract all
+ext2spice short resistor
+ext2spice merge conservative
+ext2spice cthresh 0.02
+ext2spice subcircuits top on
+ext2spice format ngspice
+ext2spice -p /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_CC -o /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_CC/inverter.pex.spice
+quit -noprompt

modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter.ext

@@ -0,0 +1,23 @@
+timestamp 0
+version 8.3
+tech ihp-sg13g2
+style ngspice()
+scale 1000 1 0.5
+resistclasses 3000000 67000 110 88 88 88 88 18 11
+parameters sg13_lv_nmos l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sg13_lv_pmos l=l w=w a1=as p1=ps a2=ad p2=pd
+port "Vout" 2 266 -211 298 -173 m1
+port "Vin" 3 95 -213 127 -175 m1
+port "Vdd" 5 -205 318 -173 356 m1
+port "Gnd" 4 20 -732 52 -694 m1
+node "ptap1_0.sub!" 0 0 28 -796 isosub 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vout" 1 392.446 266 -211 m1 0 0 0 0 91916 2354 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vin" 0 646.659 95 -213 m1 0 0 0 0 13590 482 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vdd" 1 153.076 -205 318 m1 0 0 0 0 42800 1364 0 0 0 0 0 0 0 0 0 0 0 0
+equiv "Vdd" "ntap1_0.well"
+substrate "Gnd" 0 0 20 -732 m1 0 0 0 0 21536 1036 0 0 0 0 0 0 0 0 0 0 0 0
+cap "Vin" "Vdd" 144.819
+cap "Vout" "Vin" 100.772
+cap "Vout" "Vdd" 131.55
+device msubckt sg13_lv_nmos 67 -562 68 -561 l=90 w=200 "Gnd" "Vin" 180 0 "Gnd" 200 13600,536 "Vout" 200 13600,536
+device msubckt sg13_lv_pmos 67 9 68 10 l=90 w=400 "Vdd" "Vin" 180 0 "Vdd" 400 27200,936 "Vout" 400 27200,936

modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter.res.ext

@@ -0,0 +1 @@
+scale 1000 1 0.5

modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl

@@ -0,0 +1,25 @@
+# Generated by kpex 0.3.6
+crashbackups stop
+drc off
+gds read /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/PEX_Demo/layout/inverter.gds
+load inverter
+select top cell
+flatten inverter_flat
+load inverter_flat
+cellname delete inverter -noprompt
+cellname rename inverter_flat inverter
+select top cell
+extract path /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC
+extract all
+ext2sim labels on
+ext2sim
+extresist tolerance 1
+extresist all
+ext2spice short resistor
+ext2spice merge conservative
+ext2spice cthresh 0.02
+ext2spice extresist on
+ext2spice subcircuits top on
+ext2spice format ngspice
+ext2spice -p /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC -o /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter.pex.spice
+quit -noprompt

modules/module_0_foundations/PEX_Demo/xschemrc

@@ -0,0 +1,18 @@
+# xschemrc - Custom configuration file for xschem
+# This file sources another xschemrc file from a known location
+
+# Source the base configuration from a known location
+source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
+
+# (Optional) Add any custom overrides or extensions below
+# set xschem_library_path /home/user/my_libs
+# set xschem_gui_font "Monospace 10"
+
+#### include skywater libraries. Here I use [pwd]. This works if I start xschem from here.
+###only if you dont have this setup already ### 
+###append XSCHEM_LIBRARY_PATH :[file dirname [info script]]
+
+
+#### Add custom libraries (directories with .lib files)
+append XSCHEM_LIBRARY_PATH :$PDK_ROOT/ihp-sg13g2/libs.tech/xschem
+

modules/module_0_foundations/lvs_tester/GDS/lvs_tester_extracted.cir

@@ -1,4 +1,4 @@
-* Extracted by KLayout with SG13G2 LVS runset on : 27/03/2025 11:05
+* Extracted by KLayout with SG13G2 LVS runset on : 13/02/2026 11:51
 
 .SUBCKT lvs_tester gnd G D
 M$1 gnd G D \$1 sg13_lv_nmos L=0.45u W=1u AS=0.34p AD=0.34p PS=2.68u PD=2.68u

modules/module_0_foundations/lvs_tester/schematic/simulations/lvs_tester.cdl

@@ -0,0 +1,6 @@
+** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/lvs_tester/schematic/lvs_tester.sch
+.SUBCKT lvs_tester G D gnd
+*.PININFO G:B D:B gnd:B
+M3 D G gnd sub sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+R1 gnd sub ptap1 A=6.084e-13 P=3.12e-06
+.ENDS

modules/module_1_bandgap_reference/part_1_OTA/gmid_example/testbenches/ota_testbench.sch

@@ -34,14 +34,14 @@ autoload=0
 
 sim_type=ac
 
-y2=0.029
+y2=-0.018
 y1=-160
 color=4
 node=ph(vout)
 x2=7}
 B 2 680 -1295 1480 -895 {flags=graph
-y1=-23
-y2=32
+y1=-14
+y2=30
 ypos1=0
 ypos2=2
 divy=5
@@ -60,7 +60,7 @@ logy=0
 x2=7
 color=4
 node="vout / db20()"
-}
+hcursor1_y=30.347458}
 N 775 -265 775 -235 {
 lab=vp}
 N 1010 -265 1010 -235 {
@@ -113,7 +113,7 @@ C {lab_pin.sym} 1010 -265 0 0 {name=p2 sig_type=std_logic lab=vdd}
 C {lab_pin.sym} 775 -265 0 0 {name=p3 sig_type=std_logic lab=vp}
 C {lab_pin.sym} 190 -450 0 0 {name=p5 sig_type=std_logic lab=vp}
 C {lab_pin.sym} 190 -365 0 0 {name=p6 sig_type=std_logic lab=vm}
-C {isource.sym} 270 -260 0 0 {name=I0 value=2u}
+C {isource.sym} 270 -260 0 0 {name=I0 value=80u}
 C {gnd.sym} 270 -215 0 0 {name=l3 lab=GND}
 C {capa.sym} 530 -380 0 0 {name=Cload
 m=1

slides/README.md

@@ -1,6 +1,6 @@
 # ⚠️ Disclaimer – Slides Folder
 
-The content in this folder contains **slides from the in-person Analog Academy course** held at IHP.
+The content in this folder contains **slides from the in-person Analog Academy course** hosted various places.
 
 > These slides are provided **for reference only** and are intended to **complement** the hands-on tutorials found in the `modules/` directory.