From 1a58b99dbc03e2b6aefc32c36d4483414723ab33 Mon Sep 17 00:00:00 2001
From: PhillipRambo <phillipfbp@gmail.com>
Date: Mon, 16 Feb 2026 11:25:19 +0100
Subject: [PATCH] push new slider folders

---
 .../PEX_Demo/invert_test.sch                  |  84 ++++++++++++++++++
 .../PEX_Demo/inverter_test.sym                |  26 ++++++
 .../PEX_Demo/layout/inverter.gds              | Bin 0 -> 7338 bytes
 .../PEX_Demo/layout/inverter_extracted.cir    |  10 +++
 .../PEX_Demo/layout/inverter_flat.gds         | Bin 0 -> 5766 bytes
 .../module_0_foundations/PEX_Demo/pex/kpex.sh |  32 +++++++
 .../inverter__inverter/magic_CC/inverter.ext  |  23 +++++
 .../magic_CC/inverter_MAGIC_CC_Script.tcl     |  20 +++++
 .../magic_CC/inverter_MAGIC_report.rdb.gz     | Bin 0 -> 642 bytes
 .../inverter__inverter/magic_RC/inverter.ext  |  23 +++++
 .../magic_RC/inverter.res.ext                 |   1 +
 .../magic_RC/inverter_MAGIC_RC_Script.tcl     |  25 ++++++
 .../magic_RC/inverter_MAGIC_report.rdb.gz     | Bin 0 -> 642 bytes
 .../module_0_foundations/PEX_Demo/xschemrc    |  18 ++++
 .../lvs_tester/GDS/gallery.gds                | Bin
 .../lvs_tester/GDS/lvs_tester_extracted.cir   |   2 +-
 .../lvs_tester/schematic/lvs_tester.sch       |   0
 .../schematic/simulations/lvs_tester.cdl      |   6 ++
 .../testbenches/ota_testbench.sch             |  10 +--
 slides/{day_5/test.md => Erlangen/test.py}    |   0
 .../day_1/Introduction_and_welcome_Day_1.pdf  | Bin
 .../day_2/Bandgap_reference_design_Day_2.pdf  | Bin
 .../day_3/50_GHz_mpa_Day_3.pdf                | Bin
 .../day_4/8_bit_sar_adc_Day_4.pdf             | Bin
 .../day_5/farewell_and_goodbye_Day_5.pdf      | Bin
 slides/IHP_Trial_Run_2025/day_5/test.md       |   0
 slides/README.md                              |   2 +-
 27 files changed, 275 insertions(+), 7 deletions(-)
 create mode 100644 modules/module_0_foundations/PEX_Demo/invert_test.sch
 create mode 100644 modules/module_0_foundations/PEX_Demo/inverter_test.sym
 create mode 100644 modules/module_0_foundations/PEX_Demo/layout/inverter.gds
 create mode 100644 modules/module_0_foundations/PEX_Demo/layout/inverter_extracted.cir
 create mode 100644 modules/module_0_foundations/PEX_Demo/layout/inverter_flat.gds
 create mode 100755 modules/module_0_foundations/PEX_Demo/pex/kpex.sh
 create mode 100644 modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_CC/inverter.ext
 create mode 100644 modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_CC/inverter_MAGIC_CC_Script.tcl
 create mode 100644 modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_CC/inverter_MAGIC_report.rdb.gz
 create mode 100644 modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter.ext
 create mode 100644 modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter.res.ext
 create mode 100644 modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl
 create mode 100644 modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter_MAGIC_report.rdb.gz
 create mode 100644 modules/module_0_foundations/PEX_Demo/xschemrc
 rename {utils => modules/module_0_foundations}/lvs_tester/GDS/gallery.gds (100%)
 rename {utils => modules/module_0_foundations}/lvs_tester/GDS/lvs_tester_extracted.cir (70%)
 rename {utils => modules/module_0_foundations}/lvs_tester/schematic/lvs_tester.sch (100%)
 create mode 100644 modules/module_0_foundations/lvs_tester/schematic/simulations/lvs_tester.cdl
 rename slides/{day_5/test.md => Erlangen/test.py} (100%)
 rename slides/{ => IHP_Trial_Run_2025}/day_1/Introduction_and_welcome_Day_1.pdf (100%)
 rename slides/{ => IHP_Trial_Run_2025}/day_2/Bandgap_reference_design_Day_2.pdf (100%)
 rename slides/{ => IHP_Trial_Run_2025}/day_3/50_GHz_mpa_Day_3.pdf (100%)
 rename slides/{ => IHP_Trial_Run_2025}/day_4/8_bit_sar_adc_Day_4.pdf (100%)
 rename slides/{ => IHP_Trial_Run_2025}/day_5/farewell_and_goodbye_Day_5.pdf (100%)
 create mode 100644 slides/IHP_Trial_Run_2025/day_5/test.md

diff --git a/modules/module_0_foundations/PEX_Demo/invert_test.sch b/modules/module_0_foundations/PEX_Demo/invert_test.sch
new file mode 100644
index 00000000..70efa299
--- /dev/null
+++ b/modules/module_0_foundations/PEX_Demo/invert_test.sch
@@ -0,0 +1,84 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+B 2 710 -550 1510 -150 {flags=graph
+y1=0
+y2=0.01
+ypos1=0
+ypos2=2
+divy=5
+subdivy=1
+unity=1
+x1=0
+x2=2e-06
+divx=5
+subdivx=1
+xlabmag=1.0
+ylabmag=1.0
+node=vout
+color=4
+dataset=-1
+unitx=1
+logx=0
+logy=0
+}
+N 150 -170 150 -140 {lab=Vin}
+N 70 -170 70 -140 {lab=Vdd}
+N 70 -80 70 -60 {lab=GND}
+N 110 -60 150 -60 {lab=GND}
+N 150 -80 150 -60 {lab=GND}
+N 110 -60 110 -50 {lab=GND}
+N 70 -60 110 -60 {lab=GND}
+N 320 -410 320 -380 {lab=Vdd}
+N 320 -210 320 -190 {lab=GND}
+N 220 -300 240 -300 {lab=Vin}
+N 520 -300 540 -300 {lab=Vout}
+C {vsource.sym} 150 -110 0 0 {name=V1 value="PULSE(0 1.2 0.5u 10n 10n 1u 2u 1)" savecurrent=false}
+C {vsource.sym} 70 -110 0 0 {name=V2 value=1.2 savecurrent=false}
+C {gnd.sym} 110 -50 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 150 -170 0 0 {name=p1 sig_type=std_logic lab=Vin}
+C {lab_pin.sym} 70 -170 0 0 {name=p3 sig_type=std_logic lab=Vdd}
+C {code_shown.sym} 40 -540 0 0 {name=NGSPICE
+only_toplevel=true
+value="
+.control
+save all
+tran 50n 2u 
+write test_inverter.raw
+.endc
+" }
+C {launcher.sym} 770 -120 0 0 {name=h5
+descr="load waves" 
+tclcommand="xschem raw_read $netlist_dir/test_inverter.raw tran"
+}
+C {lab_pin.sym} 220 -300 0 0 {name=p2 sig_type=std_logic lab=Vin}
+C {gnd.sym} 320 -190 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 320 -410 0 0 {name=p4 sig_type=std_logic lab=Vdd}
+C {lab_pin.sym} 540 -300 0 1 {name=p5 sig_type=std_logic lab=Vout}
+C {inverter_test.sym} 390 -300 0 0 {name=x2
+schematic=inverter
+spice_sym_def="
+* NGSPICE file created from inverter.ext - technology: ihp-sg13g2
+
+.subckt inverter Vout Vin Gnd Vdd
+X0 Vout Vin Vdd Vdd sg13_lv_pmos ad=0.68p pd=4.68u as=0.68p ps=4.68u w=2u l=0.45u
+X1 Vout Vin Gnd Gnd sg13_lv_nmos ad=0.34p pd=2.68u as=0.34p ps=2.68u w=1u l=0.45u
+C0 Vout Vdd 0.13155f
+C1 Vout Vin 0.10077f
+C2 Vin Vdd 0.14482f
+C3 Vout Gnd 0.39245f
+C4 Vin Gnd 0.64666f
+C5 Vdd Gnd 0.15308f
+.ends
+"
+}
+C {devices/code_shown.sym} 300 -540 0 0 {name=MODEL only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib cornerMOSlv.lib mos_tt
+.lib cornerRES.lib res_typ
+
+"}
diff --git a/modules/module_0_foundations/PEX_Demo/inverter_test.sym b/modules/module_0_foundations/PEX_Demo/inverter_test.sym
new file mode 100644
index 00000000..a911df0e
--- /dev/null
+++ b/modules/module_0_foundations/PEX_Demo/inverter_test.sym
@@ -0,0 +1,26 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"}
+V {}
+S {}
+E {}
+L 7 -70 -80 -70 -60 {}
+L 7 -150 0 -130 0 {}
+L 7 110 0 130 0 {}
+L 7 -70 70 -70 90 {}
+B 5 -72.5 -82.5 -67.5 -77.5 {name=Vdd dir=inout}
+B 5 -152.5 -2.5 -147.5 2.5 {name=Vin dir=inout}
+B 5 127.5 -2.5 132.5 2.5 {name=Vout dir=inout}
+B 5 -72.5 87.5 -67.5 92.5 {name=Gnd dir=inout}
+A 4 105 0 7.071067811865476 135 360 {}
+P 4 5 100 0 -130 -80 -130 90 100 0 100 0 {}
+T {@symname
+
+} -84 -6 0 0 0.3 0.3 {}
+T {@name} -45 -32 0 0 0.2 0.2 {}
+T {Vdd} -74 -55 3 1 0.2 0.2 {}
+T {Vin} -125 -4 0 0 0.2 0.2 {}
+T {Vout} 80 -9 0 1 0.2 0.2 {}
+T {Gnd} -66 65 1 1 0.2 0.2 {}
diff --git a/modules/module_0_foundations/PEX_Demo/layout/inverter.gds b/modules/module_0_foundations/PEX_Demo/layout/inverter.gds
new file mode 100644
index 0000000000000000000000000000000000000000..c5e1d2acffec04f2253a4a50adafa7e355abb3b2
GIT binary patch
literal 7338
zcmeHM-)~e!6rOwc?%ky>q!3aAHUddQtCrerr4$o>v_J`QLkToWcxh^PAxpN~rrUzV
z7at6X#+dM+iD)7rCMG@_6a52>4?Y<%@xd42fv67#6%(b!>v!hN**llz-tAI-FnXJt
zZ#gsHoHOUg%-liw%5_hwPRGsspfdPtS8LUJ`?t!ve&NWdQX5n0y(6#fdhUx4Z|^?%
z+0$3vJvE^^)A76x-|y<`Ixv28;?T*7$s<R{#_><(wJDX|;8$m6Ybw{CQu6puxhkjD
z_4>yS94Zv{=ysAlqS_(rIbVBXPj`N2f3;hYv`zQyIZwjHZlz^wxaY!rxmJSQNVD9t
zdWO0hSw?lzm@~7*QU&7Lnf%~n<=iCcG(CKk(><6(8q+*F_3!U{W+#-A)KeYQZ@PGT
z@?2@YR-Ub*eVE%)Y9qD1FjFRBe_x(Rn&om!q24kmEsokuoP*`sTxIG4XeUaQ()2>9
zXqbwuKs5H8I1HPMrE|(#ue49wHu!T3Q*(LM;MJ_QTzl2@Aj=VH(nKEY@7pzO=HuJ5
ztV`28%j31V(zNcsdzb=YJU}t)IS%>2(4fqGJIRif=F2mX5BBBryX|MVw4;Bh?hEa~
z15=gh#mdwIMeca-2#@2atu)REWJ7)Z!-Mu1r5$;rEzu{{ramz}{zE>QL!Ni#8}h`e
zKI);P+qC)yBy(3?eWcUm#J{ZiGAeN$%=*0Ad0AA<T30#BU*}@k>$O%ty$U+LO4+Y0
zjX+)H58|ixaxX&SdS^qV7SkTfXSNyRd*-JMT5UEzZQJim1VK=M&IxeegT4+yk!!U1
zzRg!-&?4_G{I*|_k45I+z;{02G2Da97Zf=#QGbe}0bQx9%&()!vCh*fYy2P4pL*4B
z31Pd}Wg(5p?TLJ{llqa}#1|BKlKsRZ`!&LT;*<RvMIN<3+u(ngtmluo(;O)NIu1q-
zu<eiV_59F5>!-XS{RW9{+BHAN`M*#39k5LKk2=^@{ml-3=N?P%-}DYWmsPGaJ$j0`
zc=QRu-HH6Vqq3V!9a*s$wCB=FE*e|Fe~>M5&S|Qjec_r~M!fYyac{+!hTn=Wv+PT*
zMZ<4p{!P}bHeXH?lJ&8xRtm1PU*iJ;J8L3UquxNPdF>UCev2F!%XhxxeuTtvUkQ=;
zrahK#^@(t`E#cU)e65#s<0akpYqi<@NY&^$QjWt`_hZ91sEiz#%m-KV@6)fx<~EzZ
zF02%+$T#Ih?4Gn=krT51TyoWJKdm3G6z3vrYNJZ6Exx!dVt-GlAAPLH&K>$~J=%Vw
zAN&VZ>i(7Lk5(%CXGQ*NUMc1T`G2KwrbH^;s)k6FP{mkncBZbjQnrMdhAeKE7g@e+
zzal4$WU9rtauGjQn5p2mlBwrQmC9-=E##X$p)u1RW~Grmt%XW4`q_WNw_MoFe}=#H
zVdK}lQq7l7(@JgFlfqfpnHt#>|IU+m<|}NTILQl!>LZyNdlJvmsSqb|Mr3#a)y5}v
z+y2$^Bb8o1#gD<-Tlc*r<JZ>Tz;`ZlKlfSY3yK_=$ajBYe(Fu;3yK_=$oEE>@7-j6
z9YsEx%um0~e1C}ff+7bd>i2(Se&%)N3yK^V%h#tz_*f(SPbcyE7m3IdzNCmpekLTp
z6JJo|N&eS7_@9vcuD=8flK)M6qW$E5>PLPjejP=g;D6$gp9#tD#1|BKlK(Xi{wE~A
z6JL=0Z`y79qdOJlH$6bATk^f2$btVDpX{SY+fVBU*>6zfz*zkc!H=FP3qkPb*Sywb
zvD2m>$NHmD<b)CZ)=rDIFXdHgjSv16L6H+O-<%2e#q6|+Uy}GT!}(O-aM`|y{gQ09
zmKs}D{3RKqzbD-F5W^O3b(-vYIo~f=aW}nCny=pz*YE!jttI5d4)$tW<Yu1Qg5Wp5
z-i90I@HRCF?p{ZXcG<1r{WG|J5Zpe?t&wk4bMNJh2f-g#vEl%O3z+fx5Je8OBNW*!
zoNt3*8LJiHJ*-yl%OQ#!n8;rmVE)oI=GRf=0}+0t+R5&_pR@h<K4tp_MGmy}NBG|L
zAozV7$`M}7+`~$Ri+e_qYmDb_(Q#8Aka#i<A>yg!64%JNQ2QUgI)Uh2V#NRUC^dp{
z42nE`Dc*iH5(K|?5>MxdQa3^rIWWO~GtVtR><-!=g5(#HN53H1f97179zc5Dz#M?f
z?*p%eC~{z<ez_|_-Yk8?@n3$6<1Z+3U@Tu1gW%^+Fn{1L^BBhqQRKiFK9v^jP6qF=
z?Y^MMhnR0x7|b8v6`S<E8Gg&X*(lao{ph>0^h+2kPb=K>vx^I@^WAOWcWZvRiZIY!
gTPyn2NAQD3{KM5^%Y5iQ1ixI=`isKH3g>z1FT@xaA^-pY

literal 0
HcmV?d00001

diff --git a/modules/module_0_foundations/PEX_Demo/layout/inverter_extracted.cir b/modules/module_0_foundations/PEX_Demo/layout/inverter_extracted.cir
new file mode 100644
index 00000000..d4acf2dc
--- /dev/null
+++ b/modules/module_0_foundations/PEX_Demo/layout/inverter_extracted.cir
@@ -0,0 +1,10 @@
+* Extracted by KLayout with SG13G2 LVS runset on : 07/07/2025 16:12
+
+.SUBCKT inverter Gnd Vout Vin Vdd
+M$1 Gnd Vin Vout \$1 sg13_lv_nmos L=0.45u W=1u AS=0.34p AD=0.34p PS=2.68u
++ PD=2.68u
+M$2 Vdd Vin Vout \$2 sg13_lv_pmos L=0.45u W=2u AS=0.68p AD=0.68p PS=4.68u
++ PD=4.68u
+R$3 \$2 Vdd ntap1 A=0.6084p P=3.12u
+R$4 \$1 Gnd ptap1 A=0.6084p P=3.12u
+.ENDS inverter
diff --git a/modules/module_0_foundations/PEX_Demo/layout/inverter_flat.gds b/modules/module_0_foundations/PEX_Demo/layout/inverter_flat.gds
new file mode 100644
index 0000000000000000000000000000000000000000..cbd1ef23804aef62b1a02f11e997cb253ca542eb
GIT binary patch
literal 5766
zcmcJTPiP!f9LL|z?#ymrZLR-8OfcqRD=69o8sb5ls03r6pd#9fU=yXKCX%LA@z7gA
z@KRC1_MmuCdJ}~T9#i!wv<D9!qzGbz$Tq2I+B81D-}igJotaJEB)j6m@>#w!-}(LC
z@BQY@n>C4vqL)lxDXK1-$aI;VW{;_7f16sAOg=Ma%w6U9@zM8&pZ(#B#>i9OKJwYw
zgD;rAIP9w@$>Et3({uCFbEZ-=Cb=y#HIwX!j4==0UN)w5z}lM^gzM*xDetmYsXAEM
zWj6O$E?K)efP<HesjefyUZv`eVShg|c^H0>e!UK<IvDUH*XNCiPYbJ8;2FhrJXMcR
zhx|O>+T}js-wAlxTBYh>AU^Z<<0SuL{u#0^ay;l~z8t5^8{;>Zr4FR(;qi-4&tv`C
z^_Ndd9MaWa=K<t({qbP_|JBd>yLyAHAM3AF9W011{_;s*cbx~2e(GVrwQH|P|B%%y
z+DB<$$?;HpYwZWtHZBO+FQrq`Po(ON;QizME5fBk@hcl%Z>($*Ka%@59>f^XE99+D
z!HX$X2RGKw`%AyT|1;u(w>~l^dN-x&V9;--tiAdT<_%n$!*wbtRR;rp#I{&7_IX~D
z+!Lkh`$B%i?X-XV_<eu4K5_SNf7(Zd{p0+|yVL&3`WNIn)$_jpJY%oN3!(9M)IX(k
z{fB>z_qnk2GUjhLzMiVLtUnn)?ynL0h4fXX#ZRgp_UGff^#?xX*751*{ViM>Wd7DF
zRd2cfTk`ko#EAGR(<$BjLl67&@m>GGuiQF5p1pX^#lyndlbHWsjZvx|59j7TlRx5P
z?2RMB<rBDn@4))wse0o`&L5}qk9y(xf8%qZeFyW1=f6^QFnj-Q@bmoA0p$G^{YtqG
zuaD#ZtN+?_={T4_^CndXH^$fX5BceN>Qk!T;!kq*<GOhU@xk@SWc^gC4rb$T@UO9N
z;a|Hb{w7r)4Ex>w;TYFJT;om<&jO|KIv9-ad_RgmdR_d=lGnjPf4Nuu<?qDbr0TuJ
z{>rTQ<DKGHsty*$$NK2TpBxguQuUVgGgp7N@9GwR75iVee^RR69ggqzKd3Xwx^o|^
zWc~f|VE)dBI+LtB{Yuu~A20N?{ydL$r@u+n3+hiF>rArl^ea^_s=xE0{v_*8zmoO$
z#|!hXqRu>z^{2l{)eGwHp8u1aKdjS#a{e+@eKI_M^sSr||Mdy+D^&-B`P09O7c0jv
z#lNaly%zSn{Ri@NME-nV;5ZyrFUX%h=1DSd`jn~{<xd~;cSPRwGk-_bgZaz8MfWMm
zAwG^d|3cNn_aD~IuhDM{Li+eVr&PVj@AmE8k_Y!sjNhc{!TyoBRh-8>TK8W~y}<AG
z|9+o-^<&IG_TkFF{yo3`{Ep}M3Va}ad~Z;y-m?GC_^o^YSeo!$l=w?Z)hELJ$GA)A
z8%OvUpMFQxy}ypB!T$$OnB*S*e~@&S4E6%|mhijY8}IM=gr75}-WQJ@gvL*u|1m_5
zqMz<IwVve7H)j2_sPk)~-*56-Guyq^1FyLcbHO}gj~b8C|JL-;qf(bGa>@8HqW3Xh
z^YkA({^~%ku0y$ff$V$Q*%xi_>;6OcBTChEU*hwJf3tbf|BJSqi*5Qh)*s6R`(j5r
ze)Quwz9rI_t_M-`9;NDJu6{ZHKYyUklh%^UAF_v1s@}-2i+j@eSkFc<SM9x*Wc<i2
z+5W!T*B}1P>c4-x{nMZ3k8yvG?{yM&8$$igDpe<Q^~?Eh{DylDb3k?t;oP56s$Lln
z``dXh@#9DQt;WCk{pb7V{_OZW&fmXRcaT5+7e)R(Ze7D~UDw9$<3fgyTg&3NF^0Xo
z|6iOvJ}>q2<KLD)8i0Sd^B<nU6!Cx6cKqfX*5?ZS<1<rj`w{zT+^nZu{3-QUah;0!
E7f#iUCIA2c

literal 0
HcmV?d00001

diff --git a/modules/module_0_foundations/PEX_Demo/pex/kpex.sh b/modules/module_0_foundations/PEX_Demo/pex/kpex.sh
new file mode 100755
index 00000000..c388ada9
--- /dev/null
+++ b/modules/module_0_foundations/PEX_Demo/pex/kpex.sh
@@ -0,0 +1,32 @@
+#!/bin/bash
+set -e
+
+# Hardcoded paths (except PDK stuff)
+
+LAYOUT_PATH="../layout/inverter.gds"
+SCHEMATIC="../simulations/inverter.spice"
+
+
+PDK_NAME="ihp_sg13g2"
+MAGICRC="$PDK_ROOT/$PDK/libs.tech/magic/ihp-sg13g2.magicrc" # The magicrc file for your PDK, used during extraction
+
+
+# Run parasitic extraction with kpex
+kpex \
+  --pdk "$PDK_NAME" \
+  --magic \
+  --schematic "$SCHEMATIC" \
+  --gds "$LAYOUT_PATH" \
+  --magicrc "$MAGICRC" \
+  --magic_mode CC \
+  --magic_cthresh 0.02 \
+  --magic_rthresh 50 \
+  --magic_short resistor \
+  --magic_merge conservative \
+  --out_dir ./pex_output
+  
+  
+  
+  
+  
+
diff --git a/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_CC/inverter.ext b/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_CC/inverter.ext
new file mode 100644
index 00000000..d094c31f
--- /dev/null
+++ b/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_CC/inverter.ext
@@ -0,0 +1,23 @@
+timestamp 0
+version 8.3
+tech ihp-sg13g2
+style ngspice()
+scale 1000 1 0.5
+resistclasses 3000000 67000 110 88 88 88 88 18 11
+parameters sg13_lv_nmos l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sg13_lv_pmos l=l w=w a1=as p1=ps a2=ad p2=pd
+port "Vout" 2 266 -211 298 -173 m1
+port "Vin" 3 95 -213 127 -175 m1
+port "Vdd" 5 -205 318 -173 356 m1
+port "Gnd" 4 20 -732 52 -694 m1
+node "ptap1_0.sub!" 0 0 28 -796 isosub 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vout" 1 392.446 266 -211 m1 0 0 0 0 91916 2354 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vin" 0 646.659 95 -213 m1 0 0 0 0 13590 482 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vdd" 1 153.076 -205 318 m1 0 0 0 0 42800 1364 0 0 0 0 0 0 0 0 0 0 0 0
+equiv "Vdd" "ntap1_0.well"
+substrate "Gnd" 0 0 20 -732 m1 0 0 0 0 21536 1036 0 0 0 0 0 0 0 0 0 0 0 0
+cap "Vout" "Vdd" 131.55
+cap "Vin" "Vdd" 144.819
+cap "Vout" "Vin" 100.772
+device msubckt sg13_lv_nmos 67 -562 68 -561 l=90 w=200 "Gnd" "Vin" 180 0 "Gnd" 200 13600,536 "Vout" 200 13600,536
+device msubckt sg13_lv_pmos 67 9 68 10 l=90 w=400 "Vdd" "Vin" 180 0 "Vdd" 400 27200,936 "Vout" 400 27200,936
diff --git a/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_CC/inverter_MAGIC_CC_Script.tcl b/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_CC/inverter_MAGIC_CC_Script.tcl
new file mode 100644
index 00000000..670a9c36
--- /dev/null
+++ b/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_CC/inverter_MAGIC_CC_Script.tcl
@@ -0,0 +1,20 @@
+# Generated by kpex 0.3.6
+crashbackups stop
+drc off
+gds read /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/PEX_Demo/layout/inverter.gds
+load inverter
+select top cell
+flatten inverter_flat
+load inverter_flat
+cellname delete inverter -noprompt
+cellname rename inverter_flat inverter
+select top cell
+extract path /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_CC
+extract all
+ext2spice short resistor
+ext2spice merge conservative
+ext2spice cthresh 0.02
+ext2spice subcircuits top on
+ext2spice format ngspice
+ext2spice -p /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_CC -o /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_CC/inverter.pex.spice
+quit -noprompt
\ No newline at end of file
diff --git a/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_CC/inverter_MAGIC_report.rdb.gz b/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_CC/inverter_MAGIC_report.rdb.gz
new file mode 100644
index 0000000000000000000000000000000000000000..01007d71b67def30607f2dcacdad62f88532f837
GIT binary patch
literal 642
zcmV-|0)71-iwFP!000001JzeckDD+Uyzj3-xnwJaS9l~TgjLm6s~)zhs;bwO7aU~O
z*a#f7{QKJGk>JpW(xu6sn9nvd_F#ETc=w!Pt%5~~DA~?z!<uQ3#56%9-Ol!Gr>|#s
z(M?#uoEA(^00U2;gwc%_Ca{bPlr#RKDQa4v6cK>+9l}tyq>#V@Fj~lp(Oi!q#!Ugz
zQasHL#DKw+Q$SJmWi1LVBp`#)!@K)W@3oK5tN^hP4NciB2PkvVR6dol<NU%GRUQ$I
zQH_wD(shL2>7Hq~nf+!!I!-%E%q<yFGgY}?>LYSd`6Rid{5|;}@~4B;A>*6vGv)Jm
z$<21%%l!Z=6u<0(ztuV1X661V{=u{dZYSQBsqH-C>XBr$ywI-u&8+gtXLat^`3g%^
z@}pThcUS(a@Fbe*fI+v?8HzA!(}ts?q(OuSB7?<o!c?F@fUq`QFsS)KuZ!-srGPtF
z@Z@YK7MjBbuH9%fK<Xm~v!+v^<~0$A!vw3Nxte@)L*|w-@6%?k`XJQ~>o_d1LM2yA
zq8-2`49%{Tec2u}lw%YlR!4Sd4(f)MW*O{VKp9B8^;ZDz`;Q`vD5tniDS4~i+J@sS
zbbh(;yr99BvGxUaH$yDP@B^)3Xq-Gyhi2#0`IfZ-dF75-hP!g59o(9>;6ANH;X9sE
z$YGPZ*5>+^yC#fSdJEg|HbIY9>!8_U3idWrI@V?Ll{;n`_Cj|I-w#^kt~gry3iSO+
zypq}TdcE>pftD(q#;f)^Wz7F@3A%a{9dTkUjkO&duqBQ%$34OJ#jMO<i<OpPxn9uY
c*1Q37{~{Y2z}v*lMfunN34klF#w8E{0P5vP<NyEw

literal 0
HcmV?d00001

diff --git a/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter.ext b/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter.ext
new file mode 100644
index 00000000..b52e7232
--- /dev/null
+++ b/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter.ext
@@ -0,0 +1,23 @@
+timestamp 0
+version 8.3
+tech ihp-sg13g2
+style ngspice()
+scale 1000 1 0.5
+resistclasses 3000000 67000 110 88 88 88 88 18 11
+parameters sg13_lv_nmos l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sg13_lv_pmos l=l w=w a1=as p1=ps a2=ad p2=pd
+port "Vout" 2 266 -211 298 -173 m1
+port "Vin" 3 95 -213 127 -175 m1
+port "Vdd" 5 -205 318 -173 356 m1
+port "Gnd" 4 20 -732 52 -694 m1
+node "ptap1_0.sub!" 0 0 28 -796 isosub 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vout" 1 392.446 266 -211 m1 0 0 0 0 91916 2354 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vin" 0 646.659 95 -213 m1 0 0 0 0 13590 482 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vdd" 1 153.076 -205 318 m1 0 0 0 0 42800 1364 0 0 0 0 0 0 0 0 0 0 0 0
+equiv "Vdd" "ntap1_0.well"
+substrate "Gnd" 0 0 20 -732 m1 0 0 0 0 21536 1036 0 0 0 0 0 0 0 0 0 0 0 0
+cap "Vin" "Vdd" 144.819
+cap "Vout" "Vin" 100.772
+cap "Vout" "Vdd" 131.55
+device msubckt sg13_lv_nmos 67 -562 68 -561 l=90 w=200 "Gnd" "Vin" 180 0 "Gnd" 200 13600,536 "Vout" 200 13600,536
+device msubckt sg13_lv_pmos 67 9 68 10 l=90 w=400 "Vdd" "Vin" 180 0 "Vdd" 400 27200,936 "Vout" 400 27200,936
diff --git a/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter.res.ext b/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter.res.ext
new file mode 100644
index 00000000..086c80d3
--- /dev/null
+++ b/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter.res.ext
@@ -0,0 +1 @@
+scale 1000 1 0.5
diff --git a/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl b/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl
new file mode 100644
index 00000000..097e7b61
--- /dev/null
+++ b/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl
@@ -0,0 +1,25 @@
+# Generated by kpex 0.3.6
+crashbackups stop
+drc off
+gds read /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/PEX_Demo/layout/inverter.gds
+load inverter
+select top cell
+flatten inverter_flat
+load inverter_flat
+cellname delete inverter -noprompt
+cellname rename inverter_flat inverter
+select top cell
+extract path /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC
+extract all
+ext2sim labels on
+ext2sim
+extresist tolerance 1
+extresist all
+ext2spice short resistor
+ext2spice merge conservative
+ext2spice cthresh 0.02
+ext2spice extresist on
+ext2spice subcircuits top on
+ext2spice format ngspice
+ext2spice -p /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC -o /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter.pex.spice
+quit -noprompt
diff --git a/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter_MAGIC_report.rdb.gz b/modules/module_0_foundations/PEX_Demo/pex/pex_output/inverter__inverter/magic_RC/inverter_MAGIC_report.rdb.gz
new file mode 100644
index 0000000000000000000000000000000000000000..01007d71b67def30607f2dcacdad62f88532f837
GIT binary patch
literal 642
zcmV-|0)71-iwFP!000001JzeckDD+Uyzj3-xnwJaS9l~TgjLm6s~)zhs;bwO7aU~O
z*a#f7{QKJGk>JpW(xu6sn9nvd_F#ETc=w!Pt%5~~DA~?z!<uQ3#56%9-Ol!Gr>|#s
z(M?#uoEA(^00U2;gwc%_Ca{bPlr#RKDQa4v6cK>+9l}tyq>#V@Fj~lp(Oi!q#!Ugz
zQasHL#DKw+Q$SJmWi1LVBp`#)!@K)W@3oK5tN^hP4NciB2PkvVR6dol<NU%GRUQ$I
zQH_wD(shL2>7Hq~nf+!!I!-%E%q<yFGgY}?>LYSd`6Rid{5|;}@~4B;A>*6vGv)Jm
z$<21%%l!Z=6u<0(ztuV1X661V{=u{dZYSQBsqH-C>XBr$ywI-u&8+gtXLat^`3g%^
z@}pThcUS(a@Fbe*fI+v?8HzA!(}ts?q(OuSB7?<o!c?F@fUq`QFsS)KuZ!-srGPtF
z@Z@YK7MjBbuH9%fK<Xm~v!+v^<~0$A!vw3Nxte@)L*|w-@6%?k`XJQ~>o_d1LM2yA
zq8-2`49%{Tec2u}lw%YlR!4Sd4(f)MW*O{VKp9B8^;ZDz`;Q`vD5tniDS4~i+J@sS
zbbh(;yr99BvGxUaH$yDP@B^)3Xq-Gyhi2#0`IfZ-dF75-hP!g59o(9>;6ANH;X9sE
z$YGPZ*5>+^yC#fSdJEg|HbIY9>!8_U3idWrI@V?Ll{;n`_Cj|I-w#^kt~gry3iSO+
zypq}TdcE>pftD(q#;f)^Wz7F@3A%a{9dTkUjkO&duqBQ%$34OJ#jMO<i<OpPxn9uY
c*1Q37{~{Y2z}v*lMfunN34klF#w8E{0P5vP<NyEw

literal 0
HcmV?d00001

diff --git a/modules/module_0_foundations/PEX_Demo/xschemrc b/modules/module_0_foundations/PEX_Demo/xschemrc
new file mode 100644
index 00000000..0d8170e0
--- /dev/null
+++ b/modules/module_0_foundations/PEX_Demo/xschemrc
@@ -0,0 +1,18 @@
+# xschemrc - Custom configuration file for xschem
+# This file sources another xschemrc file from a known location
+
+# Source the base configuration from a known location
+source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
+
+# (Optional) Add any custom overrides or extensions below
+# set xschem_library_path /home/user/my_libs
+# set xschem_gui_font "Monospace 10"
+
+#### include skywater libraries. Here I use [pwd]. This works if I start xschem from here.
+###only if you dont have this setup already ### 
+###append XSCHEM_LIBRARY_PATH :[file dirname [info script]]
+
+
+#### Add custom libraries (directories with .lib files)
+append XSCHEM_LIBRARY_PATH :$PDK_ROOT/ihp-sg13g2/libs.tech/xschem
+
diff --git a/utils/lvs_tester/GDS/gallery.gds b/modules/module_0_foundations/lvs_tester/GDS/gallery.gds
similarity index 100%
rename from utils/lvs_tester/GDS/gallery.gds
rename to modules/module_0_foundations/lvs_tester/GDS/gallery.gds
diff --git a/utils/lvs_tester/GDS/lvs_tester_extracted.cir b/modules/module_0_foundations/lvs_tester/GDS/lvs_tester_extracted.cir
similarity index 70%
rename from utils/lvs_tester/GDS/lvs_tester_extracted.cir
rename to modules/module_0_foundations/lvs_tester/GDS/lvs_tester_extracted.cir
index 6b6b6b6b..48517d9b 100644
--- a/utils/lvs_tester/GDS/lvs_tester_extracted.cir
+++ b/modules/module_0_foundations/lvs_tester/GDS/lvs_tester_extracted.cir
@@ -1,4 +1,4 @@
-* Extracted by KLayout with SG13G2 LVS runset on : 27/03/2025 11:05
+* Extracted by KLayout with SG13G2 LVS runset on : 13/02/2026 11:51
 
 .SUBCKT lvs_tester gnd G D
 M$1 gnd G D \$1 sg13_lv_nmos L=0.45u W=1u AS=0.34p AD=0.34p PS=2.68u PD=2.68u
diff --git a/utils/lvs_tester/schematic/lvs_tester.sch b/modules/module_0_foundations/lvs_tester/schematic/lvs_tester.sch
similarity index 100%
rename from utils/lvs_tester/schematic/lvs_tester.sch
rename to modules/module_0_foundations/lvs_tester/schematic/lvs_tester.sch
diff --git a/modules/module_0_foundations/lvs_tester/schematic/simulations/lvs_tester.cdl b/modules/module_0_foundations/lvs_tester/schematic/simulations/lvs_tester.cdl
new file mode 100644
index 00000000..84bec059
--- /dev/null
+++ b/modules/module_0_foundations/lvs_tester/schematic/simulations/lvs_tester.cdl
@@ -0,0 +1,6 @@
+** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/lvs_tester/schematic/lvs_tester.sch
+.SUBCKT lvs_tester G D gnd
+*.PININFO G:B D:B gnd:B
+M3 D G gnd sub sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+R1 gnd sub ptap1 A=6.084e-13 P=3.12e-06
+.ENDS
diff --git a/modules/module_1_bandgap_reference/part_1_OTA/gmid_example/testbenches/ota_testbench.sch b/modules/module_1_bandgap_reference/part_1_OTA/gmid_example/testbenches/ota_testbench.sch
index 5a4742e2..2ab6403e 100644
--- a/modules/module_1_bandgap_reference/part_1_OTA/gmid_example/testbenches/ota_testbench.sch
+++ b/modules/module_1_bandgap_reference/part_1_OTA/gmid_example/testbenches/ota_testbench.sch
@@ -34,14 +34,14 @@ autoload=0
 
 sim_type=ac
 
-y2=0.029
+y2=-0.018
 y1=-160
 color=4
 node=ph(vout)
 x2=7}
 B 2 680 -1295 1480 -895 {flags=graph
-y1=-23
-y2=32
+y1=-14
+y2=30
 ypos1=0
 ypos2=2
 divy=5
@@ -60,7 +60,7 @@ logy=0
 x2=7
 color=4
 node="vout / db20()"
-}
+hcursor1_y=30.347458}
 N 775 -265 775 -235 {
 lab=vp}
 N 1010 -265 1010 -235 {
@@ -113,7 +113,7 @@ C {lab_pin.sym} 1010 -265 0 0 {name=p2 sig_type=std_logic lab=vdd}
 C {lab_pin.sym} 775 -265 0 0 {name=p3 sig_type=std_logic lab=vp}
 C {lab_pin.sym} 190 -450 0 0 {name=p5 sig_type=std_logic lab=vp}
 C {lab_pin.sym} 190 -365 0 0 {name=p6 sig_type=std_logic lab=vm}
-C {isource.sym} 270 -260 0 0 {name=I0 value=2u}
+C {isource.sym} 270 -260 0 0 {name=I0 value=80u}
 C {gnd.sym} 270 -215 0 0 {name=l3 lab=GND}
 C {capa.sym} 530 -380 0 0 {name=Cload
 m=1
diff --git a/slides/day_5/test.md b/slides/Erlangen/test.py
similarity index 100%
rename from slides/day_5/test.md
rename to slides/Erlangen/test.py
diff --git a/slides/day_1/Introduction_and_welcome_Day_1.pdf b/slides/IHP_Trial_Run_2025/day_1/Introduction_and_welcome_Day_1.pdf
similarity index 100%
rename from slides/day_1/Introduction_and_welcome_Day_1.pdf
rename to slides/IHP_Trial_Run_2025/day_1/Introduction_and_welcome_Day_1.pdf
diff --git a/slides/day_2/Bandgap_reference_design_Day_2.pdf b/slides/IHP_Trial_Run_2025/day_2/Bandgap_reference_design_Day_2.pdf
similarity index 100%
rename from slides/day_2/Bandgap_reference_design_Day_2.pdf
rename to slides/IHP_Trial_Run_2025/day_2/Bandgap_reference_design_Day_2.pdf
diff --git a/slides/day_3/50_GHz_mpa_Day_3.pdf b/slides/IHP_Trial_Run_2025/day_3/50_GHz_mpa_Day_3.pdf
similarity index 100%
rename from slides/day_3/50_GHz_mpa_Day_3.pdf
rename to slides/IHP_Trial_Run_2025/day_3/50_GHz_mpa_Day_3.pdf
diff --git a/slides/day_4/8_bit_sar_adc_Day_4.pdf b/slides/IHP_Trial_Run_2025/day_4/8_bit_sar_adc_Day_4.pdf
similarity index 100%
rename from slides/day_4/8_bit_sar_adc_Day_4.pdf
rename to slides/IHP_Trial_Run_2025/day_4/8_bit_sar_adc_Day_4.pdf
diff --git a/slides/day_5/farewell_and_goodbye_Day_5.pdf b/slides/IHP_Trial_Run_2025/day_5/farewell_and_goodbye_Day_5.pdf
similarity index 100%
rename from slides/day_5/farewell_and_goodbye_Day_5.pdf
rename to slides/IHP_Trial_Run_2025/day_5/farewell_and_goodbye_Day_5.pdf
diff --git a/slides/IHP_Trial_Run_2025/day_5/test.md b/slides/IHP_Trial_Run_2025/day_5/test.md
new file mode 100644
index 00000000..e69de29b
diff --git a/slides/README.md b/slides/README.md
index c26c5314..42c75c33 100644
--- a/slides/README.md
+++ b/slides/README.md
@@ -1,6 +1,6 @@
 # ⚠️ Disclaimer – Slides Folder
 
-The content in this folder contains **slides from the in-person Analog Academy course** held at IHP.
+The content in this folder contains **slides from the in-person Analog Academy course** hosted various places.
 
 > These slides are provided **for reference only** and are intended to **complement** the hands-on tutorials found in the `modules/` directory.