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This commit is contained in:
PhillipRambo 2025-02-24 16:17:25 +01:00
parent 2a8f2e5f92
commit 13e47c2ca3
57 changed files with 63336 additions and 2280 deletions
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1
.gitignore vendored
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@ -6,4 +6,5 @@
*.osdi
*.dat.ngspice
*.dat
*.txt

7
modules/module_2_50GHz_MPA/part_1_biasing/schematic/bias_1_fingers/bias_1_fingers.dpl
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@ -1,6 +1,6 @@
<Qucs Schematic 24.3.1>
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75
modules/module_2_50GHz_MPA/part_1_biasing/schematic/bias_1_fingers/bias_1_fingers.sch
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@ -1,6 +1,6 @@
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@ -16,77 +16,48 @@
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20
modules/module_2_50GHz_MPA/part_1_biasing/schematic/bias_2_stability/bias_2_stability.dpl
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@ -1,6 +1,6 @@
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@ -20,23 +20,13 @@
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modules/module_2_50GHz_MPA/part_1_biasing/schematic/bias_2_stability/bias_2_stability.sch
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@ -1,11 +1,11 @@
<Qucs Schematic 24.3.1>
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@ -16,83 +16,57 @@
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2378
modules/module_2_50GHz_MPA/part_2_matching_ideal/schematic/harmonic_balance.dat.xyce Normal file
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79
modules/module_2_50GHz_MPA/part_2_matching_ideal/schematic/input_matching.sch Normal file
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@ -0,0 +1,79 @@
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106
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41
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103
modules/module_2_50GHz_MPA/part_2_matching_ideal/schematic/output_matching/output_matching.sch
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46226
modules/module_2_50GHz_MPA/part_3_nonlinear_analysis/compression_point/schematic/harmonic_balance.dat.xyce Normal file
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97
modules/module_2_50GHz_MPA/part_3_nonlinear_analysis/compression_point/schematic/harmonic_balance.sch Normal file
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11658
modules/module_2_50GHz_MPA/part_3_nonlinear_analysis/load_pull/schematic/load_pull_real_part.dat.xyce Normal file
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modules/module_2_50GHz_MPA/part_3_nonlinear_analysis/load_pull/schematic/load_pull_real_part.sch Normal file
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<Qucs Schematic 24.3.1>
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82
modules/module_2_50GHz_MPA/part_3_nonlinear_analysis/load_pull/schematic/load_pull_real_part_matched.sch Normal file
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<Qucs Schematic 24.3.1>
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modules/module_2_50GHz_MPA/part_3_nonlinear_analysis/schematic/harmonic_balancing.dat.xyce
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0
modules/module_2_50GHz_MPA/part_3_nonlinear_analysis/schematic/harmonic_balancing.dpl
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modules/module_2_50GHz_MPA/part_3_nonlinear_analysis/schematic/harmonic_balancing.sch
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modules/module_3_8_bit_SAR_ADC/part_1_comparator/test_benches/comparator_offset_single_sim.sch
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C {lab_pin.sym} 60 -280 2 1 {name=p5 sig_type=std_logic lab=vip}
C {lab_pin.sym} 200 -350 2 0 {name=p6 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 60 -220 2 1 {name=p7 sig_type=std_logic lab=vbias}
C {lab_pin.sym} 60 -160 2 1 {name=p8 sig_type=std_logic lab=vbias}
C {lab_pin.sym} 250 -110 2 0 {name=p9 sig_type=std_logic lab=clk}
C {gnd.sym} 200 -90 0 0 {name=l3 lab=GND}
C {lab_pin.sym} 500 -230 2 0 {name=p10 sig_type=std_logic lab=outp}
C {lab_pin.sym} 500 -210 2 0 {name=p11 sig_type=std_logic lab=outm}
C {capa.sym} 80 -110 0 0 {name=C1
m=1
value=16.384p
footprint=1206
device="ceramic capacitor"}
C {gnd.sym} 80 -60 0 0 {name=l4 lab=GND}
C {gnd.sym} 80 -380 2 0 {name=l5 lab=GND}
C {capa.sym} 80 -330 2 0 {name=C2
m=1
value=16.384p
footprint=1206
device="ceramic capacitor"}
C {capa.sym} 460 -260 2 0 {name=C4
m=1
value=15f
footprint=1206
device="ceramic capacitor"}
C {capa.sym} 460 -180 0 0 {name=C3
m=1
value=15f
footprint=1206
device="ceramic capacitor"}
C {gnd.sym} 460 -140 0 0 {name=l6 lab=GND}
C {gnd.sym} 460 -300 2 0 {name=l7 lab=GND}
C {launcher.sym} 170 -630 0 0 {name=h5
descr="load waves"
tclcommand="xschem raw_read $netlist_dir/output_file.raw tran"
}
C {devices/code_shown.sym} -735 -1130 0 0 {name=NGSPICE only_toplevel=false
value="
.control
op
.param clock = 100e6 ; 100 MHz clock
.param period = 1 / clock
.param num_cycles = 80 ; number of evaluation cycles
.param tr = num_cycles * period
tran 300p 800n
save all
; Define vdiff as the output differential voltage
let vdiff = v(outp) - v(outm)
; Measure when vdiff = 0.65V
meas tran cross_time WHEN vdiff = 0.65 RISE=1
; define input differentially also
let vindiff = v(vip) - v(vbias)
; Measure the difference of the input
meas tran offset_voltage find vindiff at=cross_time RISE=1
let save_offset_voltage = offset_voltage
print save_offset_voltage > vbe_tempvar.txt
write output.raw
.endc
"}

2
modules/module_3_8_bit_SAR_ADC/part_1_comparator/test_benches/comparator_tb.sch
View File

@ -52,7 +52,7 @@ x2=1e-06
color=4
node=v+}
node=vinp}
B 2 850 -1225 1650 -825 {flags=graph
y1=-1.3
y2=1.3

137
modules/module_3_8_bit_SAR_ADC/part_1_comparator/test_benches/comparator_tb_test.sch
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@ -1,137 +0,0 @@
v {xschem version=3.4.5 file_version=1.2
}
G {}
K {}
V {}
S {}
E {}
N -540 -180 -540 -160 {
lab=vbias}
N -610 -180 -610 -160 {
lab=vdd}
N -610 -100 -610 -80 {
lab=GND}
N -570 -80 -540 -80 {
lab=GND}
N -420 -180 -420 -160 {
lab=clk}
N -420 -100 -420 -70 {
lab=GND}
N -570 -80 -570 -70 {
lab=GND}
N -420 -70 -210 -70 {
lab=GND}
N -210 -100 -210 -70 {
lab=GND}
N -210 -180 -210 -160 {
lab=vip}
N 60 -220 120 -220 {
lab=vbias}
N 200 -120 200 -90 {
lab=GND}
N 250 -140 250 -110 {
lab=clk}
N 200 -350 200 -320 {
lab=vdd}
N 400 -210 500 -210 {
lab=outm}
N 400 -230 500 -230 {
lab=outp}
N 80 -160 120 -160 {
lab=vbias}
N 80 -280 120 -280 {
lab=vip}
N -610 -80 -570 -80 {
lab=GND}
N -540 -100 -540 -80 {
lab=GND}
N 80 -300 80 -280 {
lab=vip}
N 60 -280 80 -280 {
lab=vip}
N 80 -160 80 -140 {
lab=vbias}
N 60 -160 80 -160 {
lab=vbias}
N 80 -80 80 -60 {
lab=GND}
N 80 -380 80 -360 {
lab=GND}
N 460 -150 460 -140 {
lab=GND}
N 460 -300 460 -290 {
lab=GND}
C {devices/code_shown.sym} -685 -530 0 0 {name=MODEL only_toplevel=false
format="tcleval( @value )"
value="
.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ
.lib cornerMOSlv.lib mos_tt
"}
C {vsource.sym} -610 -130 0 0 {name=V3 value="DC 1.2"}
C {vsource.sym} -540 -130 0 0 {name=V4 value="DC 0.6"}
C {gnd.sym} -310 -70 0 0 {name=l1 lab=GND}
C {lab_pin.sym} -540 -180 2 0 {name=p3 sig_type=std_logic lab=vbias}
C {lab_pin.sym} -610 -180 2 0 {name=p4 sig_type=std_logic lab=vdd}
C {vsource.sym} -420 -130 0 0 {name=V1 value="PULSE(0 1.2 0 0 0 5N \{period\})"}
C {lab_pin.sym} -420 -180 2 0 {name=p1 sig_type=std_logic lab=clk}
C {gnd.sym} -570 -70 0 0 {name=l2 lab=GND}
C {vsource.sym} -210 -130 0 0 {name=V2 value="PULSE(595e-3 605e-3 0 tr 1S 1S"}
C {lab_pin.sym} -210 -180 2 0 {name=p2 sig_type=std_logic lab=vip}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_1_comparator/schematic/dynamic_comparator.sym} 270 -220 0 0 {name=x1}
C {lab_pin.sym} 60 -280 2 1 {name=p5 sig_type=std_logic lab=vip}
C {lab_pin.sym} 200 -350 2 0 {name=p6 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 60 -220 2 1 {name=p7 sig_type=std_logic lab=vbias}
C {lab_pin.sym} 60 -160 2 1 {name=p8 sig_type=std_logic lab=vbias}
C {lab_pin.sym} 250 -110 2 0 {name=p9 sig_type=std_logic lab=clk}
C {gnd.sym} 200 -90 0 0 {name=l3 lab=GND}
C {lab_pin.sym} 500 -230 2 0 {name=p10 sig_type=std_logic lab=outp}
C {lab_pin.sym} 500 -210 2 0 {name=p11 sig_type=std_logic lab=outm}
C {capa.sym} 80 -110 0 0 {name=C1
m=1
value=16.384p
footprint=1206
device="ceramic capacitor"}
C {gnd.sym} 80 -60 0 0 {name=l4 lab=GND}
C {gnd.sym} 80 -380 2 0 {name=l5 lab=GND}
C {capa.sym} 80 -330 2 0 {name=C2
m=1
value=16.384p
footprint=1206
device="ceramic capacitor"}
C {capa.sym} 460 -260 2 0 {name=C4
m=1
value=15f
footprint=1206
device="ceramic capacitor"}
C {capa.sym} 460 -180 0 0 {name=C3
m=1
value=15f
footprint=1206
device="ceramic capacitor"}
C {gnd.sym} 460 -140 0 0 {name=l6 lab=GND}
C {gnd.sym} 460 -300 2 0 {name=l7 lab=GND}
C {devices/code_shown.sym} -705 -1010 0 0 {name=NGSPICE only_toplevel=false
value="
.control
let run = 1
let mc_runs = 10
let results = unitvec(mc_runs)
dowhile run <= mc_runs
reset
.param clock = 100e6 ; 100 MHz clock
.param period = 1 / clock
.param num_cycles = 80 ; number of evaluation cycles
.param tr = num_cycles * period
tran 300p 800n
set run = $&run
let vdiff = v(outp) - v(outm)
meas tran cross_time WHEN vdiff = 0.65 RISE=1
let vindiff = v(vip) - v(vbias)
meas tran offset_voltage_\{$run\} find vindiff at=cross_time RISE=1
let results[$run - 1] = offset_voltage_\{$run\}
let run = run + 1
end
print results > vbe_tempvar.txt
.endc
"}

10
modules/module_3_8_bit_SAR_ADC/part_1_comparator/test_benches/offset_MC_analysis.sch
View File

@ -104,24 +104,24 @@ footprint=1206
device="ceramic capacitor"}
C {gnd.sym} 460 -140 0 0 {name=l6 lab=GND}
C {gnd.sym} 460 -300 2 0 {name=l7 lab=GND}
C {devices/code_shown.sym} -395 -440 0 0 {name=MODEL1 only_toplevel=false
C {devices/code_shown.sym} 15 -480 0 0 {name=MODEL1 only_toplevel=false
format="tcleval( @value )"
value="
.lib cornerMOSlv.lib mos_tt_mismatch
"}
C {devices/code_shown.sym} 85 -930 0 0 {name=NGSPICE1 only_toplevel=false
C {devices/code_shown.sym} -675 -780 0 0 {name=NGSPICE1 only_toplevel=false
value="
.control
let run = 1
let mc_runs = 400
let mc_runs = 100
let results = unitvec(mc_runs)
dowhile run <= mc_runs
reset
.param clock = 100e6 ; 100 MHz clock
.param period = 1 / clock
.param num_cycles = 100 ; number of evaluation cycles
.param num_cycles = 200 ; number of evaluation cycles
.param tr = num_cycles * period
tran 300p 1u
tran 300p 2u
set run = $&run
let vdiff = v(outp) - v(outm)

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24
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/dig.v Normal file
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@ -0,0 +1,24 @@
module dig(
input wire clk,
input wire reset,
output logic [4:0] b
);
logic rst = 0;
always_ff @(posedge clk) begin
if(reset)
rst <= 1;
else
rst <= 0;
end
always_ff @(posedge clk) begin
if(rst)
b <= 0;
else
b <= b + 1;
end // dig
endmodule

112
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/dig_obj_dir/Vlng.cpp Normal file
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@ -0,0 +1,112 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vlng.h for the primary calling header
#include "Vlng.h"
#include "Vlng__Syms.h"
//==========
void Vlng::eval_step() {
VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vlng::eval\n"); );
Vlng__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
#ifdef VL_DEBUG
// Debug assertions
_eval_debug_assertions();
#endif // VL_DEBUG
// Initialize
if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
// Evaluate till stable
int __VclockLoop = 0;
QData __Vchange = 1;
do {
VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n"););
_eval(vlSymsp);
if (VL_UNLIKELY(++__VclockLoop > 100)) {
// About to fail, so enable debug to see what's not settling.
// Note you must run make with OPT=-DVL_DEBUG for debug prints.
int __Vsaved_debug = Verilated::debug();
Verilated::debug(1);
__Vchange = _change_request(vlSymsp);
Verilated::debug(__Vsaved_debug);
VL_FATAL_MT("dig.v", 1, "",
"Verilated model didn't converge\n"
"- See DIDNOTCONVERGE in the Verilator manual");
} else {
__Vchange = _change_request(vlSymsp);
}
} while (VL_UNLIKELY(__Vchange));
}
void Vlng::_eval_initial_loop(Vlng__Syms* __restrict vlSymsp) {
vlSymsp->__Vm_didInit = true;
_eval_initial(vlSymsp);
// Evaluate till stable
int __VclockLoop = 0;
QData __Vchange = 1;
do {
_eval_settle(vlSymsp);
_eval(vlSymsp);
if (VL_UNLIKELY(++__VclockLoop > 100)) {
// About to fail, so enable debug to see what's not settling.
// Note you must run make with OPT=-DVL_DEBUG for debug prints.
int __Vsaved_debug = Verilated::debug();
Verilated::debug(1);
__Vchange = _change_request(vlSymsp);
Verilated::debug(__Vsaved_debug);
VL_FATAL_MT("dig.v", 1, "",
"Verilated model didn't DC converge\n"
"- See DIDNOTCONVERGE in the Verilator manual");
} else {
__Vchange = _change_request(vlSymsp);
}
} while (VL_UNLIKELY(__Vchange));
}
VL_INLINE_OPT void Vlng::_sequent__TOP__1(Vlng__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::_sequent__TOP__1\n"); );
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->b = ((IData)(vlTOPp->dig__DOT__rst) ? 0U
: (0x1fU & ((IData)(1U) + (IData)(vlTOPp->b))));
vlTOPp->dig__DOT__rst = vlTOPp->reset;
}
void Vlng::_eval(Vlng__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::_eval\n"); );
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) {
vlTOPp->_sequent__TOP__1(vlSymsp);
}
// Final
vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
}
VL_INLINE_OPT QData Vlng::_change_request(Vlng__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::_change_request\n"); );
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
return (vlTOPp->_change_request_1(vlSymsp));
}
VL_INLINE_OPT QData Vlng::_change_request_1(Vlng__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::_change_request_1\n"); );
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
// Change detection
QData __req = false; // Logically a bool
return __req;
}
#ifdef VL_DEBUG
void Vlng::_eval_debug_assertions() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::_eval_debug_assertions\n"); );
// Body
if (VL_UNLIKELY((clk & 0xfeU))) {
Verilated::overWidthError("clk");}
if (VL_UNLIKELY((reset & 0xfeU))) {
Verilated::overWidthError("reset");}
}
#endif // VL_DEBUG

88
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/dig_obj_dir/Vlng.h Normal file
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@ -0,0 +1,88 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary design header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef _VLNG_H_
#define _VLNG_H_ // guard
#include "verilated.h"
//==========
class Vlng__Syms;
//----------
VL_MODULE(Vlng) {
public:
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
VL_IN8(clk,0,0);
VL_IN8(reset,0,0);
VL_OUT8(b,4,0);
// LOCAL SIGNALS
// Internals; generally not touched by application code
CData/*0:0*/ dig__DOT__rst;
// LOCAL VARIABLES
// Internals; generally not touched by application code
CData/*0:0*/ __Vclklast__TOP__clk;
// INTERNAL VARIABLES
// Internals; generally not touched by application code
Vlng__Syms* __VlSymsp; // Symbol table
// CONSTRUCTORS
private:
VL_UNCOPYABLE(Vlng); ///< Copying not allowed
public:
/// Construct the model; called by application code
/// The special name may be used to make a wrapper with a
/// single model invisible with respect to DPI scope names.
Vlng(const char* name = "TOP");
/// Destroy the model; called (often implicitly) by application code
~Vlng();
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval() { eval_step(); }
/// Evaluate when calling multiple units/models per time step.
void eval_step();
/// Evaluate at end of a timestep for tracing, when using eval_step().
/// Application must call after all eval() and before time changes.
void eval_end_step() {}
/// Simulation complete, run final blocks. Application must call on completion.
void final();
// INTERNAL METHODS
private:
static void _eval_initial_loop(Vlng__Syms* __restrict vlSymsp);
public:
void __Vconfigure(Vlng__Syms* symsp, bool first);
private:
static QData _change_request(Vlng__Syms* __restrict vlSymsp);
static QData _change_request_1(Vlng__Syms* __restrict vlSymsp);
void _ctor_var_reset() VL_ATTR_COLD;
public:
static void _eval(Vlng__Syms* __restrict vlSymsp);
private:
#ifdef VL_DEBUG
void _eval_debug_assertions();
#endif // VL_DEBUG
public:
static void _eval_initial(Vlng__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _eval_settle(Vlng__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _initial__TOP__2(Vlng__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _sequent__TOP__1(Vlng__Syms* __restrict vlSymsp);
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
//----------
#endif // guard

71
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/dig_obj_dir/Vlng.mk Normal file
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@ -0,0 +1,71 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f Vlng.mk
default: Vlng
### Constants...
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
### Switches...
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# Legacy or SystemC output mode? 0/1 (from --sc)
VM_SP_OR_SC = $(VM_SC)
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = Vlng
# Module prefix (from --prefix)
VM_MODPREFIX = Vlng
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
-I/usr/local/share/ngspice/scripts/src \
-fpic \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
verilator_main \
verilator_shim \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
/usr/local/share/ngspice/scripts/src \
### Default rules...
# Include list of all generated classes
include Vlng_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
### Executable rules... (from --exe)
VPATH += $(VM_USER_DIR)
verilator_main.o: /usr/local/share/ngspice/scripts/src/verilator_main.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
verilator_shim.o: /usr/local/share/ngspice/scripts/src/verilator_shim.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
### Link rules... (from --exe)
Vlng: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a
$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) $(LIBS) $(SC_LIBS) -o $@
# Verilated -*- Makefile -*-

65
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/dig_obj_dir/Vlng__Slow.cpp Normal file
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@ -0,0 +1,65 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vlng.h for the primary calling header
#include "Vlng.h"
#include "Vlng__Syms.h"
//==========
VL_CTOR_IMP(Vlng) {
Vlng__Syms* __restrict vlSymsp = __VlSymsp = new Vlng__Syms(this, name());
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void Vlng::__Vconfigure(Vlng__Syms* vlSymsp, bool first) {
if (false && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
if (false && this->__VlSymsp) {} // Prevent unused
Verilated::timeunit(-12);
Verilated::timeprecision(-12);
}
Vlng::~Vlng() {
VL_DO_CLEAR(delete __VlSymsp, __VlSymsp = NULL);
}
void Vlng::_initial__TOP__2(Vlng__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::_initial__TOP__2\n"); );
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->dig__DOT__rst = 0U;
}
void Vlng::_eval_initial(Vlng__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::_eval_initial\n"); );
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
vlTOPp->_initial__TOP__2(vlSymsp);
}
void Vlng::final() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::final\n"); );
// Variables
Vlng__Syms* __restrict vlSymsp = this->__VlSymsp;
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}
void Vlng::_eval_settle(Vlng__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::_eval_settle\n"); );
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}
void Vlng::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::_ctor_var_reset\n"); );
// Body
clk = VL_RAND_RESET_I(1);
reset = VL_RAND_RESET_I(1);
b = VL_RAND_RESET_I(5);
dig__DOT__rst = VL_RAND_RESET_I(1);
}

21
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/dig_obj_dir/Vlng__Syms.cpp Normal file
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@ -0,0 +1,21 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "Vlng__Syms.h"
#include "Vlng.h"
// FUNCTIONS
Vlng__Syms::Vlng__Syms(Vlng* topp, const char* namep)
// Setup locals
: __Vm_namep(namep)
, __Vm_didInit(false)
// Setup submodule names
{
// Pointer to top level
TOPp = topp;
// Setup each module's pointers to their submodules
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
}

35
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/dig_obj_dir/Vlng__Syms.h Normal file
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@ -0,0 +1,35 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header,
// unless using verilator public meta comments.
#ifndef _VLNG__SYMS_H_
#define _VLNG__SYMS_H_ // guard
#include "verilated.h"
// INCLUDE MODULE CLASSES
#include "Vlng.h"
// SYMS CLASS
class Vlng__Syms : public VerilatedSyms {
public:
// LOCAL STATE
const char* __Vm_namep;
bool __Vm_didInit;
// SUBCELL STATE
Vlng* TOPp;
// CREATORS
Vlng__Syms(Vlng* topp, const char* namep);
~Vlng__Syms() {}
// METHODS
inline const char* name() { return __Vm_namep; }
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
#endif // guard

1
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/dig_obj_dir/Vlng__ver.d Normal file
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dig_obj_dir/Vlng.cpp dig_obj_dir/Vlng.h dig_obj_dir/Vlng.mk dig_obj_dir/Vlng__Slow.cpp dig_obj_dir/Vlng__Syms.cpp dig_obj_dir/Vlng__Syms.h dig_obj_dir/Vlng__ver.d dig_obj_dir/Vlng_classes.mk : /usr/bin/verilator_bin /usr/bin/verilator_bin dig.v

47
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/dig_obj_dir/Vlng_classes.mk Normal file
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# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See Vlng.mk for the caller.
### Switches...
# C11 constructs required? 0/1 (from --threads, --trace-threads or use of classes)
VM_C11 = 0
# Coverage output mode? 0/1 (from --coverage)
VM_COVERAGE = 0
# Parallel builds? 0/1 (from --output-split)
VM_PARALLEL_BUILDS = 0
# Threaded output mode? 0/1/N threads (from --threads)
VM_THREADS = 0
# Tracing output mode? 0/1 (from --trace/--trace-fst)
VM_TRACE = 0
# Tracing threaded output mode? 0/1/N threads (from --trace-thread)
VM_TRACE_THREADS = 0
# Separate FST writer thread? 0/1 (from --trace-fst with --trace-thread > 0)
VM_TRACE_FST_WRITER_THREAD = 0
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
Vlng \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
Vlng__Slow \
# Generated support classes, fast-path, compile with highest optimization
VM_SUPPORT_FAST += \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
Vlng__Syms \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \
verilated \
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
VM_GLOBAL_SLOW += \
# Verilated -*- Makefile -*-

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modules/module_3_8_bit_SAR_ADC/part_3_algorithm/dig_obj_dir/inouts.h Normal file
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/* Generated code: do not edit. */

3
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/dig_obj_dir/inputs.h Normal file
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/* Generated code: do not edit. */
VL_DATA(8,lk,0,0)
VL_DATA(8,eset,0,0)

2
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/dig_obj_dir/outputs.h Normal file
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/* Generated code: do not edit. */
VL_DATA(8,,4,0)

4
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/dig_obj_dir/verilator_main.d Normal file
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verilator_main.o: /usr/local/share/ngspice/scripts/src/verilator_main.cpp \
/usr/local/share/ngspice/scripts/src/ngspice/cmtypes.h \
/usr/local/share/ngspice/scripts/src/ngspice/miftypes.h \
/usr/local/share/ngspice/scripts/src/ngspice/cosim.h

BIN
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/dig_obj_dir/verilator_main.o Normal file
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Binary file not shown.

7
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/dig_obj_dir/verilator_shim.d Normal file
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verilator_shim.o: /usr/local/share/ngspice/scripts/src/verilator_shim.cpp \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilatedos.h Vlng.h \
/usr/local/share/ngspice/scripts/src/ngspice/cmtypes.h \
/usr/local/share/ngspice/scripts/src/ngspice/miftypes.h \
/usr/local/share/ngspice/scripts/src/ngspice/cosim.h outputs.h inouts.h \
inputs.h

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modules/module_3_8_bit_SAR_ADC/part_3_algorithm/sar_algo.v Normal file
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//Verilog HDL for "8_bit_SAR_ADC", "sar_algorithm" "functional"
module sar_algorithm (
input wire Op,
input wire En,
input wire Om,
input wire clk,
input wire rst,
output reg [7:0] B, // 8-bit
output reg [7:0] BN, // 8-bit
output reg [7:0] D // 8-bit
);
reg [2:0] counter = 3'b000; // 3-bit counter
always @(posedge clk) begin
if (En && !rst && (Op ^ Om)) begin
if (counter != 3'b111) begin // Limit to 8
D[counter] <= Op;
if (Op) begin
B[counter] <= 1'b1;
BN[counter] <= 1'b0;
end else if (Om) begin
B[counter] <= 1'b0;
BN[counter] <= 1'b1;
end
counter <= counter + 1'b1;
end
end else if (rst) begin
B <= 8'b00000000;
BN <= 8'b00000000;
D <= 8'b00000000;
counter <= 3'b000;
end
end
endmodule

146
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/sar_algo_obj_dir/Vlng.cpp Normal file
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vlng.h for the primary calling header
#include "Vlng.h"
#include "Vlng__Syms.h"
//==========
void Vlng::eval_step() {
VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vlng::eval\n"); );
Vlng__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
#ifdef VL_DEBUG
// Debug assertions
_eval_debug_assertions();
#endif // VL_DEBUG
// Initialize
if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
// Evaluate till stable
int __VclockLoop = 0;
QData __Vchange = 1;
do {
VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n"););
_eval(vlSymsp);
if (VL_UNLIKELY(++__VclockLoop > 100)) {
// About to fail, so enable debug to see what's not settling.
// Note you must run make with OPT=-DVL_DEBUG for debug prints.
int __Vsaved_debug = Verilated::debug();
Verilated::debug(1);
__Vchange = _change_request(vlSymsp);
Verilated::debug(__Vsaved_debug);
VL_FATAL_MT("sar_algo.v", 3, "",
"Verilated model didn't converge\n"
"- See DIDNOTCONVERGE in the Verilator manual");
} else {
__Vchange = _change_request(vlSymsp);
}
} while (VL_UNLIKELY(__Vchange));
}
void Vlng::_eval_initial_loop(Vlng__Syms* __restrict vlSymsp) {
vlSymsp->__Vm_didInit = true;
_eval_initial(vlSymsp);
// Evaluate till stable
int __VclockLoop = 0;
QData __Vchange = 1;
do {
_eval_settle(vlSymsp);
_eval(vlSymsp);
if (VL_UNLIKELY(++__VclockLoop > 100)) {
// About to fail, so enable debug to see what's not settling.
// Note you must run make with OPT=-DVL_DEBUG for debug prints.
int __Vsaved_debug = Verilated::debug();
Verilated::debug(1);
__Vchange = _change_request(vlSymsp);
Verilated::debug(__Vsaved_debug);
VL_FATAL_MT("sar_algo.v", 3, "",
"Verilated model didn't DC converge\n"
"- See DIDNOTCONVERGE in the Verilator manual");
} else {
__Vchange = _change_request(vlSymsp);
}
} while (VL_UNLIKELY(__Vchange));
}
VL_INLINE_OPT void Vlng::_sequent__TOP__1(Vlng__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::_sequent__TOP__1\n"); );
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
if ((((IData)(vlTOPp->En) & (~ (IData)(vlTOPp->rst)))
& ((IData)(vlTOPp->Op) ^ (IData)(vlTOPp->Om)))) {
if ((7U != (IData)(vlTOPp->sar_algorithm__DOT__counter))) {
vlTOPp->D = (((~ ((IData)(1U) << (IData)(vlTOPp->sar_algorithm__DOT__counter)))
& (IData)(vlTOPp->D)) | ((IData)(vlTOPp->Op)
<< (IData)(vlTOPp->sar_algorithm__DOT__counter)));
if (vlTOPp->Op) {
vlTOPp->B = ((IData)(vlTOPp->B) | ((IData)(1U)
<< (IData)(vlTOPp->sar_algorithm__DOT__counter)));
vlTOPp->BN = ((~ ((IData)(1U) << (IData)(vlTOPp->sar_algorithm__DOT__counter)))
& (IData)(vlTOPp->BN));
} else {
if (vlTOPp->Om) {
vlTOPp->B = ((~ ((IData)(1U) << (IData)(vlTOPp->sar_algorithm__DOT__counter)))
& (IData)(vlTOPp->B));
vlTOPp->BN = ((IData)(vlTOPp->BN)
| ((IData)(1U) << (IData)(vlTOPp->sar_algorithm__DOT__counter)));
}
}
vlTOPp->sar_algorithm__DOT__counter = (7U
& ((IData)(1U)
+ (IData)(vlTOPp->sar_algorithm__DOT__counter)));
}
} else {
if (vlTOPp->rst) {
vlTOPp->sar_algorithm__DOT__counter = 0U;
vlTOPp->B = 0U;
vlTOPp->BN = 0U;
vlTOPp->D = 0U;
}
}
}
void Vlng::_eval(Vlng__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::_eval\n"); );
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) {
vlTOPp->_sequent__TOP__1(vlSymsp);
}
// Final
vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
}
VL_INLINE_OPT QData Vlng::_change_request(Vlng__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::_change_request\n"); );
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
return (vlTOPp->_change_request_1(vlSymsp));
}
VL_INLINE_OPT QData Vlng::_change_request_1(Vlng__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::_change_request_1\n"); );
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
// Change detection
QData __req = false; // Logically a bool
return __req;
}
#ifdef VL_DEBUG
void Vlng::_eval_debug_assertions() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::_eval_debug_assertions\n"); );
// Body
if (VL_UNLIKELY((Op & 0xfeU))) {
Verilated::overWidthError("Op");}
if (VL_UNLIKELY((En & 0xfeU))) {
Verilated::overWidthError("En");}
if (VL_UNLIKELY((Om & 0xfeU))) {
Verilated::overWidthError("Om");}
if (VL_UNLIKELY((clk & 0xfeU))) {
Verilated::overWidthError("clk");}
if (VL_UNLIKELY((rst & 0xfeU))) {
Verilated::overWidthError("rst");}
}
#endif // VL_DEBUG

93
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/sar_algo_obj_dir/Vlng.h Normal file
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary design header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef _VLNG_H_
#define _VLNG_H_ // guard
#include "verilated.h"
//==========
class Vlng__Syms;
//----------
VL_MODULE(Vlng) {
public:
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
VL_IN8(clk,0,0);
VL_IN8(Op,0,0);
VL_IN8(En,0,0);
VL_IN8(Om,0,0);
VL_IN8(rst,0,0);
VL_OUT8(B,7,0);
VL_OUT8(BN,7,0);
VL_OUT8(D,7,0);
// LOCAL SIGNALS
// Internals; generally not touched by application code
CData/*2:0*/ sar_algorithm__DOT__counter;
// LOCAL VARIABLES
// Internals; generally not touched by application code
CData/*0:0*/ __Vclklast__TOP__clk;
// INTERNAL VARIABLES
// Internals; generally not touched by application code
Vlng__Syms* __VlSymsp; // Symbol table
// CONSTRUCTORS
private:
VL_UNCOPYABLE(Vlng); ///< Copying not allowed
public:
/// Construct the model; called by application code
/// The special name may be used to make a wrapper with a
/// single model invisible with respect to DPI scope names.
Vlng(const char* name = "TOP");
/// Destroy the model; called (often implicitly) by application code
~Vlng();
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval() { eval_step(); }
/// Evaluate when calling multiple units/models per time step.
void eval_step();
/// Evaluate at end of a timestep for tracing, when using eval_step().
/// Application must call after all eval() and before time changes.
void eval_end_step() {}
/// Simulation complete, run final blocks. Application must call on completion.
void final();
// INTERNAL METHODS
private:
static void _eval_initial_loop(Vlng__Syms* __restrict vlSymsp);
public:
void __Vconfigure(Vlng__Syms* symsp, bool first);
private:
static QData _change_request(Vlng__Syms* __restrict vlSymsp);
static QData _change_request_1(Vlng__Syms* __restrict vlSymsp);
void _ctor_var_reset() VL_ATTR_COLD;
public:
static void _eval(Vlng__Syms* __restrict vlSymsp);
private:
#ifdef VL_DEBUG
void _eval_debug_assertions();
#endif // VL_DEBUG
public:
static void _eval_initial(Vlng__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _eval_settle(Vlng__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _initial__TOP__2(Vlng__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _sequent__TOP__1(Vlng__Syms* __restrict vlSymsp);
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
//----------
#endif // guard

71
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/sar_algo_obj_dir/Vlng.mk Normal file
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# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f Vlng.mk
default: Vlng
### Constants...
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
### Switches...
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# Legacy or SystemC output mode? 0/1 (from --sc)
VM_SP_OR_SC = $(VM_SC)
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = Vlng
# Module prefix (from --prefix)
VM_MODPREFIX = Vlng
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
-I/usr/local/share/ngspice/scripts/src \
-fpic \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
verilator_main \
verilator_shim \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
/usr/local/share/ngspice/scripts/src \
### Default rules...
# Include list of all generated classes
include Vlng_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
### Executable rules... (from --exe)
VPATH += $(VM_USER_DIR)
verilator_main.o: /usr/local/share/ngspice/scripts/src/verilator_main.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
verilator_shim.o: /usr/local/share/ngspice/scripts/src/verilator_shim.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
### Link rules... (from --exe)
Vlng: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a
$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) $(LIBS) $(SC_LIBS) -o $@
# Verilated -*- Makefile -*-

70
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/sar_algo_obj_dir/Vlng__Slow.cpp Normal file
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vlng.h for the primary calling header
#include "Vlng.h"
#include "Vlng__Syms.h"
//==========
VL_CTOR_IMP(Vlng) {
Vlng__Syms* __restrict vlSymsp = __VlSymsp = new Vlng__Syms(this, name());
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void Vlng::__Vconfigure(Vlng__Syms* vlSymsp, bool first) {
if (false && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
if (false && this->__VlSymsp) {} // Prevent unused
Verilated::timeunit(-12);
Verilated::timeprecision(-12);
}
Vlng::~Vlng() {
VL_DO_CLEAR(delete __VlSymsp, __VlSymsp = NULL);
}
void Vlng::_initial__TOP__2(Vlng__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::_initial__TOP__2\n"); );
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->sar_algorithm__DOT__counter = 0U;
}
void Vlng::_eval_initial(Vlng__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::_eval_initial\n"); );
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
vlTOPp->_initial__TOP__2(vlSymsp);
}
void Vlng::final() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::final\n"); );
// Variables
Vlng__Syms* __restrict vlSymsp = this->__VlSymsp;
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}
void Vlng::_eval_settle(Vlng__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::_eval_settle\n"); );
Vlng* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}
void Vlng::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng::_ctor_var_reset\n"); );
// Body
Op = VL_RAND_RESET_I(1);
En = VL_RAND_RESET_I(1);
Om = VL_RAND_RESET_I(1);
clk = VL_RAND_RESET_I(1);
rst = VL_RAND_RESET_I(1);
B = VL_RAND_RESET_I(8);
BN = VL_RAND_RESET_I(8);
D = VL_RAND_RESET_I(8);
sar_algorithm__DOT__counter = VL_RAND_RESET_I(3);
}

21
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/sar_algo_obj_dir/Vlng__Syms.cpp Normal file
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "Vlng__Syms.h"
#include "Vlng.h"
// FUNCTIONS
Vlng__Syms::Vlng__Syms(Vlng* topp, const char* namep)
// Setup locals
: __Vm_namep(namep)
, __Vm_didInit(false)
// Setup submodule names
{
// Pointer to top level
TOPp = topp;
// Setup each module's pointers to their submodules
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
}

35
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/sar_algo_obj_dir/Vlng__Syms.h Normal file
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header,
// unless using verilator public meta comments.
#ifndef _VLNG__SYMS_H_
#define _VLNG__SYMS_H_ // guard
#include "verilated.h"
// INCLUDE MODULE CLASSES
#include "Vlng.h"
// SYMS CLASS
class Vlng__Syms : public VerilatedSyms {
public:
// LOCAL STATE
const char* __Vm_namep;
bool __Vm_didInit;
// SUBCELL STATE
Vlng* TOPp;
// CREATORS
Vlng__Syms(Vlng* topp, const char* namep);
~Vlng__Syms() {}
// METHODS
inline const char* name() { return __Vm_namep; }
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
#endif // guard

1
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/sar_algo_obj_dir/Vlng__ver.d Normal file
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@ -0,0 +1 @@
sar_algo_obj_dir/Vlng.cpp sar_algo_obj_dir/Vlng.h sar_algo_obj_dir/Vlng.mk sar_algo_obj_dir/Vlng__Slow.cpp sar_algo_obj_dir/Vlng__Syms.cpp sar_algo_obj_dir/Vlng__Syms.h sar_algo_obj_dir/Vlng__ver.d sar_algo_obj_dir/Vlng_classes.mk : /usr/bin/verilator_bin /usr/bin/verilator_bin sar_algo.v

47
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/sar_algo_obj_dir/Vlng_classes.mk Normal file
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# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See Vlng.mk for the caller.
### Switches...
# C11 constructs required? 0/1 (from --threads, --trace-threads or use of classes)
VM_C11 = 0
# Coverage output mode? 0/1 (from --coverage)
VM_COVERAGE = 0
# Parallel builds? 0/1 (from --output-split)
VM_PARALLEL_BUILDS = 0
# Threaded output mode? 0/1/N threads (from --threads)
VM_THREADS = 0
# Tracing output mode? 0/1 (from --trace/--trace-fst)
VM_TRACE = 0
# Tracing threaded output mode? 0/1/N threads (from --trace-thread)
VM_TRACE_THREADS = 0
# Separate FST writer thread? 0/1 (from --trace-fst with --trace-thread > 0)
VM_TRACE_FST_WRITER_THREAD = 0
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
Vlng \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
Vlng__Slow \
# Generated support classes, fast-path, compile with highest optimization
VM_SUPPORT_FAST += \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
Vlng__Syms \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \
verilated \
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
VM_GLOBAL_SLOW += \
# Verilated -*- Makefile -*-

1
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/sar_algo_obj_dir/inouts.h Normal file
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@ -0,0 +1 @@
/* Generated code: do not edit. */

6
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/sar_algo_obj_dir/inputs.h Normal file
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@ -0,0 +1,6 @@
/* Generated code: do not edit. */
VL_DATA(8,lk,0,0)
VL_DATA(8,p,0,0)
VL_DATA(8,n,0,0)
VL_DATA(8,m,0,0)
VL_DATA(8,st,0,0)

4
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/sar_algo_obj_dir/outputs.h Normal file
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@ -0,0 +1,4 @@
/* Generated code: do not edit. */
VL_DATA(8,,7,0)
VL_DATA(8,N,7,0)
VL_DATA(8,,7,0)

4
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/sar_algo_obj_dir/verilator_main.d Normal file
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verilator_main.o: /usr/local/share/ngspice/scripts/src/verilator_main.cpp \
/usr/local/share/ngspice/scripts/src/ngspice/cmtypes.h \
/usr/local/share/ngspice/scripts/src/ngspice/miftypes.h \
/usr/local/share/ngspice/scripts/src/ngspice/cosim.h

BIN
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/sar_algo_obj_dir/verilator_main.o Normal file
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Binary file not shown.

7
modules/module_3_8_bit_SAR_ADC/part_3_algorithm/sar_algo_obj_dir/verilator_shim.d Normal file
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verilator_shim.o: /usr/local/share/ngspice/scripts/src/verilator_shim.cpp \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilatedos.h Vlng.h \
/usr/local/share/ngspice/scripts/src/ngspice/cmtypes.h \
/usr/local/share/ngspice/scripts/src/ngspice/miftypes.h \
/usr/local/share/ngspice/scripts/src/ngspice/cosim.h outputs.h inouts.h \
inputs.h