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PhillipRambo
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@ -1,12 +0,0 @@
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** OTA_SIMPLE flat netlist
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*.PININFO V-:B V+:B VSS:B VDD:B IOUT:B VOUT:B
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M4 NET3 NET1 VSS VSS SG13_LV_NMOS L=9.75U W=720N NG=1 M=1
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M3 NET1 NET1 VSS VSS SG13_LV_NMOS L=9.75U W=720N NG=1 M=1
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M1 NET1 V- NET2 VDD SG13_LV_PMOS L=3.64U W=7.41U NG=1 M=1
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M2 NET3 V+ NET2 VDD SG13_LV_PMOS L=3.64U W=7.41U NG=1 M=1
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M5 NET2 IOUT VDD VDD SG13_LV_PMOS L=1.95U W=5.3U NG=1 M=1
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M7 VOUT IOUT VDD VDD SG13_LV_PMOS L=2.08U W=75U NG=8 M=1
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M6 VOUT NET3 VSS VSS SG13_LV_NMOS L=9.75U W=28.8U NG=4 M=1
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M9 IOUT IOUT VDD VDD SG13_LV_PMOS L=2.08U W=75U NG=8 M=1
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C2 NET3 VOUT CAP_CMIM W=22.295E-6 L=22.295E-6 M=1
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.end
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@ -1,101 +0,0 @@
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** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/ota_testbench.sch
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**.subckt ota_testbench vout vout1 vout2 vout3
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*.iopin vout
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*.iopin vout1
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*.iopin vout2
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*.iopin vout3
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x1 vdd net1 vp vm vout GND two_stage_OTA
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V1 vp GND DC 0.6 AC 1 0
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VDD vdd GND DC 1.2
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I0 net1 GND 80u
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Cload vout GND 500f m=1
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L6 vout vm 4G m=1
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C1 vm GND 4G m=1
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x2 vdd net2 vp vp vout1 GND two_stage_OTA
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I1 net2 GND 80u
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Cload1 vout1 GND 500f m=1
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x3 VDDac net3 net4 vm vout2 GND two_stage_OTA
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I2 net3 GND 80u
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L13 vout2 vm 4G m=1
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C2 vm GND 4G m=1
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V2 VDDac GND DC 1.2 AC 1 0
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V4 net4 GND DC 0.6
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XU1 vout3 vp net5 diff_amp_cell
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L16 vout3 net5 4G m=1
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C3 net5 GND 4G m=1
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**** begin user architecture code
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.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerCAP.lib cap_typ
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.lib cornerMOSlv.lib mos_tt
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.control
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op
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save all
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write tb_OTA_op.raw
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.endc
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.control
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op
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ac dec 100 1 10e6
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save all
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let Av = db(v(vout))
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let PSRR = db(v(vout2)/v(VDDac))
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let CMRR = db((v(vout)/v(vp))/(v(vout1)/v(vp)))
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let phase = 180*cph(vout)/pi
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write output_file.raw
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.endc
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**** end user architecture code
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**.ends
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* expanding symbol: two_stage_OTA.sym # of pins=6
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** sym_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sym
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** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sch
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.subckt two_stage_OTA vdd iout v+ v- vout vss
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*.iopin v-
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*.iopin v+
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*.iopin vss
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*.iopin vdd
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*.iopin iout
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*.iopin vout
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XM4 net3 net1 vss vss sg13_lv_nmos w=720n l=9.75u ng=1 m=1
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XM3 net1 net1 vss vss sg13_lv_nmos w=720n l=9.75u ng=1 m=1
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XM1 net1 v- net2 vdd sg13_lv_pmos w=27.84u l=3.25u ng=4 m=1
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XM2 net3 v+ net2 vdd sg13_lv_pmos w=27.84u l=3.25u ng=4 m=1
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XM5 net2 iout vdd vdd sg13_lv_pmos w=5.3u l=1.95u ng=1 m=1
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XM7 vout iout vdd vdd sg13_lv_pmos w=75u l=2.08u ng=8 m=1
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XM6 vout net3 vss vss sg13_lv_nmos w=28.8u l=9.75u ng=4 m=1
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XM9 iout iout vdd vdd sg13_lv_pmos w=75u l=2.08u ng=8 m=1
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XC2 net3 vout cap_cmim w=22.295e-6 l=22.295e-6 m=1
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.ends
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.GLOBAL GND
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**** begin user architecture code
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.subckt diff_amp_cell OUT IN1 IN2
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N1 out in1 in2 diff_amp_model
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.ends diff_amp_cell
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.model diff_amp_model diff_amp
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.control
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* following line specifies the location for the .osdi file so ngspice can use it.
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pre_osdi /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/diff_amp.osdi
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.endc
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**** end user architecture code
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.end
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File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
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@ -217,7 +217,6 @@ N 1180 160 1180 330 {
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lab=#net5}
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N 1110 80 1210 80 {
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lab=vp}
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C {two_stage_OTA.sym} 360 -410 0 0 {name=x1}
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C {vsource.sym} 775 -205 0 0 {name=V1 value="DC 0.6 AC 1 0"
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}
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C {vsource.sym} 1010 -205 0 0 {name=VDD value="DC 1.2"}
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@ -277,7 +276,6 @@ C {launcher.sym} 420 -635 0 0 {name=h5
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descr="load waves"
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tclcommand="xschem raw_read $netlist_dir/output_file.raw ac"
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}
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C {two_stage_OTA.sym} 1305 -255 0 0 {name=x2}
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C {gnd.sym} 1290 -170 0 0 {name=l8 lab=GND}
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C {lab_pin.sym} 1290 -335 0 0 {name=p4 sig_type=std_logic lab=vdd}
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C {lab_pin.sym} 1135 -295 0 0 {name=p10 sig_type=std_logic lab=vp}
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@ -290,7 +288,6 @@ footprint=1206
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device="ceramic capacitor"}
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C {gnd.sym} 1475 -180 0 0 {name=l10 lab=GND}
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C {iopin.sym} 1565 -255 0 0 {name=p12 lab=vout1}
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C {two_stage_OTA.sym} 350 240 0 0 {name=x3}
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C {gnd.sym} 335 325 0 0 {name=l4 lab=GND}
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C {lab_pin.sym} 180 285 0 0 {name=p11 sig_type=std_logic lab=vm}
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C {isource.sym} 260 390 0 0 {name=I2 value=80u}
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@ -328,3 +325,6 @@ device="ceramic capacitor"}
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C {gnd.sym} 1180 400 0 0 {name=l17 lab=GND}
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C {iopin.sym} 1570 120 0 0 {name=p9 lab=vout3}
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C {lab_pin.sym} 1110 80 0 0 {name=p14 sig_type=std_logic lab=vp}
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C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sym} 350 240 0 0 {name=x4}
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C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sym} 360 -410 0 0 {name=x1}
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C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sym} 1305 -255 0 0 {name=x2}
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@ -0,0 +1,98 @@
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v {xschem version=3.4.5 file_version=1.2
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}
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G {}
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K {}
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V {}
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S {}
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E {}
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N 725 -405 725 -375 {
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lab=vp}
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N 960 -405 960 -375 {
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lab=vdd}
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N 960 -315 960 -295 {
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lab=GND}
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N 835 -295 960 -295 {
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lab=GND}
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N 295 -485 295 -465 {
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lab=GND}
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N 295 -630 295 -615 {
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lab=vdd}
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N 140 -590 160 -590 {
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lab=vp}
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N 140 -505 160 -505 {
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lab=vout}
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N 480 -490 480 -475 {
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lab=GND}
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N 160 -505 160 -250 {
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lab=vout}
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N 835 -295 835 -275 {
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lab=GND}
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N 725 -295 835 -295 {
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lab=GND}
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N 725 -315 725 -295 {
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lab=GND}
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N 540 -550 570 -550 {
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lab=vout}
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N 540 -550 540 -250 {
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lab=vout}
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N 460 -550 540 -550 {
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lab=vout}
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N 220 -465 220 -430 {
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lab=#net1}
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N 220 -370 220 -355 {
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lab=GND}
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N 160 -250 540 -250 {
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lab=vout}
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C {vsource.sym} 725 -345 0 0 {name=V1 value="DC 0.6 AC 1 0"
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}
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C {vsource.sym} 960 -345 0 0 {name=VDD value="DC 1.2"}
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C {gnd.sym} 835 -275 0 0 {name=l1 lab=GND}
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C {gnd.sym} 295 -465 0 0 {name=l2 lab=GND}
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C {lab_pin.sym} 295 -630 0 0 {name=p1 sig_type=std_logic lab=vdd}
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C {lab_pin.sym} 960 -405 0 0 {name=p2 sig_type=std_logic lab=vdd}
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C {lab_pin.sym} 725 -405 0 0 {name=p3 sig_type=std_logic lab=vp}
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C {lab_pin.sym} 140 -590 0 0 {name=p5 sig_type=std_logic lab=vp}
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C {isource.sym} 220 -400 0 0 {name=I0 value=80u}
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C {gnd.sym} 220 -355 0 0 {name=l3 lab=GND}
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C {capa.sym} 480 -520 0 0 {name=Cload
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m=1
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value=500f
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footprint=1206
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device="ceramic capacitor"}
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C {gnd.sym} 480 -475 0 0 {name=l5 lab=GND}
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C {iopin.sym} 570 -550 0 0 {name=p7 lab=vout}
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C {devices/code_shown.sym} 95 -770 0 0 {name=MODEL only_toplevel=false
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format="tcleval( @value )"
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value="
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.lib cornerCAP.lib cap_typ
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.lib cornerMOSlv.lib mos_tt_mismatch
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"}
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C {devices/code_shown.sym} 25 -1260 0 0 {name=NGSPICE only_toplevel=false
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value="
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.control
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let run = 1
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let mc_runs = 100
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set curplot = new
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set scratch = $curplot
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dowhile run <= mc_runs
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reset
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dc temp 0 70 5
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set run = $&run
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set dc = $curplot
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setplot $scratch
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let off\{$run\} = \{$dc\}.v(vout)
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let mytemp\{$run\} = \\"\{$dc\}.temp-sweep\\"
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setplot $dc
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let run = run + 1
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end
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set nolegend
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plot \{$scratch\}.allv vs \{$scratch\}.mytemp1
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write ota_testbench_mc_mis.raw \{$scratch\}.allv \{$scratch\}.mytemp1
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.endc
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"}
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C {launcher.sym} 430 -635 0 0 {name=h5
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descr="load waves"
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tclcommand="xschem raw_read $netlist_dir/output_file.raw ac"
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}
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C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sym} 310 -550 0 0 {name=x1}
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Binary file not shown.
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@ -1,75 +1,31 @@
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* Extracted by KLayout with SG13G2 LVS runset on : 13/12/2024 15:39
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* Extracted by KLayout with SG13G2 LVS runset on : 13/02/2025 13:18
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.SUBCKT two_stage_OTA_layout
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M$1 \$2 \$70 \$3 \$1 sg13_lv_nmos L=9.75u W=7.2u AS=2.448p AD=1.368p PS=15.08u
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+ PD=7.58u
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M$2 \$3 \$73 \$4 \$1 sg13_lv_nmos L=9.75u W=7.2u AS=1.368p AD=1.368p PS=7.58u
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+ PD=7.58u
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M$3 \$4 \$8 \$5 \$1 sg13_lv_nmos L=9.75u W=7.2u AS=1.368p AD=1.368p PS=7.58u
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+ PD=7.58u
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M$4 \$5 \$8 \$6 \$1 sg13_lv_nmos L=9.75u W=7.2u AS=1.368p AD=2.448p PS=7.58u
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+ PD=15.08u
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M$5 \$9 \$70 \$10 \$69 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
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+ PS=7.96u PD=7.96u
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M$6 \$11 \$70 \$12 \$71 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
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+ PS=7.96u PD=7.96u
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M$7 \$13 \$73 \$14 \$72 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
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+ PS=7.96u PD=7.96u
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M$8 \$15 \$73 \$16 \$74 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
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+ PS=7.96u PD=7.96u
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M$9 \$37 \$86 \$38 \$85 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
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+ PS=7.96u PD=7.96u
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M$10 \$39 \$88 \$40 \$87 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
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+ PS=7.96u PD=7.96u
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M$11 \$41 \$91 \$42 \$90 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
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+ PS=7.96u PD=7.96u
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M$12 \$43 \$93 \$44 \$92 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
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+ PS=7.96u PD=7.96u
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M$13 \$49 \$83 \$50 \$82 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
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+ PS=7.96u PD=7.96u
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M$14 \$51 \$81 \$52 \$80 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
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+ PS=7.96u PD=7.96u
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M$15 \$53 \$79 \$54 \$78 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
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+ PS=7.96u PD=7.96u
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M$16 \$55 \$76 \$56 \$77 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
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+ PS=7.96u PD=7.96u
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M$17 \$17 \$8 \$18 \$94 sg13_lv_pmos L=1.95u W=5.3u AS=1.802p AD=1.802p
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.SUBCKT two_stage_OTA_layout vss vdd dn3 iout vout dn2 v+ v\x2d vss$1 dn4
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M$1 vss dn3 dn3 vss sg13_lv_nmos L=9.75u W=0.72u AS=0.2448p AD=0.2448p PS=2.12u
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+ PD=2.12u
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M$2 vss dn3 dn4 vss sg13_lv_nmos L=9.75u W=0.72u AS=0.2448p AD=0.2448p PS=2.12u
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+ PD=2.12u
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M$3 vss$1 dn4 vout vss sg13_lv_nmos L=9.75u W=28.8u AS=6.552p AD=6.552p
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+ PS=37.82u PD=37.82u
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M$7 vdd iout iout \$3 sg13_lv_pmos L=2.08u W=75u AS=15.65625p AD=15.65625p
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+ PS=87.715u PD=87.715u
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M$15 vdd iout vout \$3 sg13_lv_pmos L=2.08u W=75u AS=15.65625p AD=15.65625p
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+ PS=87.715u PD=87.715u
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M$23 vdd vdd dn2 \$2 sg13_lv_pmos L=3.7u W=14.56u AS=4.9504p AD=4.9504p
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+ PS=31.84u PD=31.84u
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M$25 dn2 v+ dn4 \$2 sg13_lv_pmos L=3.7u W=7.28u AS=2.4752p AD=2.4752p PS=15.92u
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+ PD=15.92u
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M$26 dn2 v\x2d dn3 \$2 sg13_lv_pmos L=3.7u W=7.28u AS=2.4752p AD=2.4752p
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+ PS=15.92u PD=15.92u
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M$27 dn4 vdd vdd \$2 sg13_lv_pmos L=3.7u W=7.28u AS=2.4752p AD=2.4752p
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+ PS=15.92u PD=15.92u
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M$28 dn3 vdd vdd \$2 sg13_lv_pmos L=3.7u W=7.28u AS=2.4752p AD=2.4752p
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+ PS=15.92u PD=15.92u
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M$35 dn2 iout vdd \$38 sg13_lv_pmos L=1.95u W=5.3u AS=1.802p AD=1.802p
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+ PS=11.28u PD=11.28u
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M$18 \$45 \$98 \$46 \$99 sg13_lv_pmos L=1.95u W=5.3u AS=1.802p AD=1.802p
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+ PS=11.28u PD=11.28u
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M$19 \$47 \$95 \$48 \$97 sg13_lv_pmos L=1.95u W=5.3u AS=1.802p AD=1.802p
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+ PS=11.28u PD=11.28u
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M$20 \$19 \$8 \$20 \$108 sg13_lv_pmos L=2.08u W=9.375u AS=3.1875p AD=1.78125p
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+ PS=19.43u PD=9.755u
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M$21 \$20 \$8 \$21 \$108 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p AD=1.78125p
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+ PS=9.755u PD=9.755u
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M$22 \$21 \$8 \$22 \$108 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p AD=1.78125p
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+ PS=9.755u PD=9.755u
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M$23 \$22 \$8 \$23 \$108 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p AD=1.78125p
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+ PS=9.755u PD=9.755u
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M$24 \$23 \$8 \$24 \$108 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p AD=1.78125p
|
||||
+ PS=9.755u PD=9.755u
|
||||
M$25 \$24 \$8 \$25 \$108 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p AD=1.78125p
|
||||
+ PS=9.755u PD=9.755u
|
||||
M$26 \$25 \$8 \$26 \$108 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p AD=1.78125p
|
||||
+ PS=9.755u PD=9.755u
|
||||
M$27 \$26 \$106 \$27 \$108 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p AD=3.1875p
|
||||
+ PS=9.755u PD=19.43u
|
||||
M$28 \$28 \$107 \$29 \$104 sg13_lv_pmos L=2.08u W=9.375u AS=3.1875p AD=1.78125p
|
||||
+ PS=19.43u PD=9.755u
|
||||
M$29 \$29 \$110 \$30 \$104 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p
|
||||
+ AD=1.78125p PS=9.755u PD=9.755u
|
||||
M$30 \$30 \$109 \$31 \$104 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p
|
||||
+ AD=1.78125p PS=9.755u PD=9.755u
|
||||
M$31 \$31 \$111 \$32 \$104 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p
|
||||
+ AD=1.78125p PS=9.755u PD=9.755u
|
||||
M$32 \$32 \$112 \$33 \$104 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p
|
||||
+ AD=1.78125p PS=9.755u PD=9.755u
|
||||
M$33 \$33 \$113 \$34 \$104 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p
|
||||
+ AD=1.78125p PS=9.755u PD=9.755u
|
||||
M$34 \$34 \$105 \$35 \$104 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p
|
||||
+ AD=1.78125p PS=9.755u PD=9.755u
|
||||
M$35 \$35 \$103 \$36 \$104 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p AD=3.1875p
|
||||
+ PS=9.755u PD=19.43u
|
||||
C$36 \$102 \$101 cap_cmim w=22.295u l=22.295u A=497.067025p P=89.18u m=1
|
||||
C$36 \$7 vout cap_cmim w=22.295u l=22.295u A=497.067025p P=89.18u m=1
|
||||
R$37 \$3 vdd ntap1 A=27.435p P=177u
|
||||
R$38 \$2 vdd ntap1 A=28.7556p P=185.52u
|
||||
R$39 \$38 vdd ntap1 A=7.5826p P=48.92u
|
||||
R$40 vss vss$1 ptap1 A=25.19p P=201.52u
|
||||
.ENDS two_stage_OTA_layout
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
* Extracted by KLayout with SG13G2 LVS runset on : 07/01/2025 13:14
|
||||
* Extracted by KLayout with SG13G2 LVS runset on : 13/02/2025 13:49
|
||||
|
||||
.SUBCKT input_common_centroid v\x2d vdd v+ dn4 dn3
|
||||
M$1 vdd vdd \$7 \$3 sg13_lv_pmos L=3.7u W=14.56u AS=4.9504p AD=4.9504p
|
||||
|
|
@ -11,5 +11,5 @@ M$5 \$7 v\x2d dn3 \$3 sg13_lv_pmos L=3.7u W=7.28u AS=2.4752p AD=2.4752p
|
|||
+ PS=15.92u PD=15.92u
|
||||
M$6 dn3 vdd vdd \$3 sg13_lv_pmos L=3.7u W=7.28u AS=2.4752p AD=2.4752p PS=15.92u
|
||||
+ PD=15.92u
|
||||
R$13 \$3 vdd ntap1 A=169.1692p P=241.12u
|
||||
R$13 \$3 vdd ntap1 A=197.9248p P=243.6u
|
||||
.ENDS input_common_centroid
|
||||
|
|
|
|||
|
|
@ -1,12 +1,10 @@
|
|||
* Extracted by KLayout with SG13G2 LVS runset on : 29/01/2025 15:40
|
||||
* Extracted by KLayout with SG13G2 LVS runset on : 13/02/2025 13:49
|
||||
|
||||
.SUBCKT input_stage vss dn4 dn3 vdd dn2 iout
|
||||
M$1 vss dn3 dn4 \$1 sg13_lv_nmos L=9.75u W=0.72u AS=0.2448p AD=0.2448p PS=2.12u
|
||||
+ PD=2.12u
|
||||
M$2 vss dn3 dn3 \$1 sg13_lv_nmos L=9.75u W=0.72u AS=0.2448p AD=0.2448p PS=2.12u
|
||||
+ PD=2.12u
|
||||
M$3 dn2 iout vdd \$8 sg13_lv_pmos L=1.95u W=5.3u AS=1.802p AD=1.802p PS=11.28u
|
||||
.SUBCKT input_stage dn3|dn4|vss vdd dn2 iout
|
||||
M$1 dn3|dn4|vss dn3|dn4|vss dn3|dn4|vss \$1 sg13_lv_nmos L=9.75u W=1.44u
|
||||
+ AS=0.4896p AD=0.4896p PS=4.24u PD=4.24u
|
||||
M$3 dn2 iout vdd \$6 sg13_lv_pmos L=1.95u W=5.3u AS=1.802p AD=1.802p PS=11.28u
|
||||
+ PD=11.28u
|
||||
R$4 \$8 vdd ntap1 A=7.5826p P=48.92u
|
||||
R$5 \$1 vss ptap1 A=7.0975p P=56.78u
|
||||
R$4 \$6 vdd ntap1 A=21.5031p P=43.5u
|
||||
R$5 \$1 dn3|dn4|vss ptap1 A=15.54345p P=53.44u
|
||||
.ENDS input_stage
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
<Qucs Schematic 24.3.1>
|
||||
<Properties>
|
||||
<View=-67,-9,1324,1021,1.0813,0,0>
|
||||
<View=-351,1,1571,1130,0.782108,0,0>
|
||||
<Grid=10,10,0>
|
||||
<DataSet=output_matching.dat>
|
||||
<DataDisplay=output_matching.sch>
|
||||
|
|
@ -22,12 +22,20 @@
|
|||
<Diagrams>
|
||||
<Smith 1 623 582 582 3 #c0c0c0 1 00 1 0 1 1 1 0 4 1 1 0 1 1 315 0 225 1 0 0 "" "" "">
|
||||
<"ngspice/ac.v(s_1_1)" #0000ff 0 3 0 0 0>
|
||||
<Mkr 5e+10 401 -309 3 0 0>
|
||||
<Mkr 4.5e+10 401 -309 3 0 0>
|
||||
</Smith>
|
||||
<Smith 661 623 582 582 3 #c0c0c0 1 00 1 0 1 1 1 0 4 1 1 0 1 1 315 0 225 1 0 0 "" "" "">
|
||||
<"ngspice/ac.v(s_2_2)" #e01b24 0 3 0 0 0>
|
||||
<Mkr 5e+10 350 -357 3 0 0>
|
||||
<Mkr 4.55e+10 350 -357 3 0 0>
|
||||
</Smith>
|
||||
<Rect 40 1038 527 317 3 #c0c0c0 1 01 0 4.5e+10 1e+09 5.5e+10 1 0.01 1 1 1 -1 0.5 1 315 0 225 1 1 0 "" "" "">
|
||||
<"ngspice/ac.v(s_1_1)" #0000ff 0 3 0 0 0>
|
||||
<Mkr 4.5e+10 385 -103 3 0 0>
|
||||
</Rect>
|
||||
<Rect 700 1038 527 317 3 #c0c0c0 1 01 0 4.5e+10 1e+09 5.5e+10 1 0.001 1 1 1 -1 0.5 1 315 0 225 1 1 0 "" "" "">
|
||||
<"ngspice/ac.v(s_2_2)" #ff0000 0 3 0 0 0>
|
||||
<Mkr 5.5e+10 374 -83 3 0 0>
|
||||
</Rect>
|
||||
</Diagrams>
|
||||
<Paintings>
|
||||
</Paintings>
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
<Qucs Schematic 24.3.1>
|
||||
<Properties>
|
||||
<View=-662,-134,850,683,0.994048,0,0>
|
||||
<View=-717,-198,985,870,0.883,0,0>
|
||||
<Grid=10,10,1>
|
||||
<DataSet=output_matching.dat>
|
||||
<DataDisplay=output_matching.dpl>
|
||||
|
|
@ -34,7 +34,6 @@
|
|||
<L L22 1 300 400 -26 10 0 0 "Lstab" 1 "" 0>
|
||||
<L L24 1 -70 410 -96 -26 0 3 "Lin" 1 "" 0>
|
||||
<L L25 1 -70 320 -96 -26 0 3 "Lin" 1 "" 0>
|
||||
<.SP SP1 1 -260 -80 0 61 0 0 "lin" 1 "1 GHz" 1 "300 GHz" 1 "1197" 1 "no" 0 "1" 0 "2" 0 "no" 0 "no" 0>
|
||||
<.DC DC1 1 -100 -80 0 36 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0>
|
||||
<INCLSCR INCLSCR1 1 -200 90 -60 16 0 0 ".LIB cornerHBT.lib hbt_typ\n" 1 "" 0 "" 0>
|
||||
<NutmegEq NutmegEq1 1 -290 570 -28 16 0 0 "SP1" 1 "k=(1 - abs(s_1_1)^2 - abs(s_2_2)^2 + abs(s_1_1 * s_2_2 - s_1_2 * s_2_1)^2) / (2 * abs(s_1_2 * s_2_1))\n" 1>
|
||||
|
|
@ -42,7 +41,7 @@
|
|||
<C C26 1 -150 480 -20 -49 0 2 "Cin" 1 "" 0 "neutral" 0>
|
||||
<SpicePar SpicePar1 1 -370 10 -28 16 0 0 "Lstab=300pH" 1>
|
||||
<SpicePar SpicePar3 1 -370 90 -28 16 0 0 "Lin=254.5pH" 1>
|
||||
<SpicePar SpicePar2 1 -480 90 -28 16 0 0 "Cin=36.974fF" 1>
|
||||
<SpicePar SpicePar2 1 -480 90 -28 16 0 0 "Cin=45fF" 1>
|
||||
<SpicePar SpicePar4 1 -480 10 -28 16 0 0 "Cout=88fF" 1>
|
||||
<SpicePar SpicePar5 1 -590 10 -28 16 0 0 "Lout=273pH" 1>
|
||||
<L L28 1 360 50 -96 -26 0 3 "Lout" 1 "" 0>
|
||||
|
|
@ -51,6 +50,7 @@
|
|||
<C C30 1 570 100 -20 -49 0 2 "Cout" 1 "" 0 "neutral" 0>
|
||||
<GND * 1 690 180 0 0 0 0>
|
||||
<L L30 1 170 400 -26 10 0 0 "Lstab" 1 "" 0>
|
||||
<.SP SP1 1 -260 -80 0 61 0 0 "lin" 1 "45 GHz" 1 "55 GHz" 1 "41" 1 "no" 0 "1" 0 "2" 0 "no" 0 "no" 0>
|
||||
</Components>
|
||||
<Wires>
|
||||
<110 320 110 400 "VE" 50 300 27 "">
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,119 @@
|
|||
<Qucs Schematic 24.3.1>
|
||||
<Properties>
|
||||
<View=-500,-170,1643,988,0.701209,0,0>
|
||||
<Grid=10,10,1>
|
||||
<DataSet=harmonic_balancing.dat>
|
||||
<DataDisplay=harmonic_balancing.dpl>
|
||||
<OpenDisplay=0>
|
||||
<Script=harmonic_balancing.m>
|
||||
<RunScript=0>
|
||||
<showFrame=0>
|
||||
<FrameText0=Title>
|
||||
<FrameText1=Drawn By:>
|
||||
<FrameText2=Date:>
|
||||
<FrameText3=Revision:>
|
||||
</Properties>
|
||||
<Symbol>
|
||||
</Symbol>
|
||||
<Components>
|
||||
<GND * 1 570 420 0 0 0 0>
|
||||
<Vdc V2 1 570 370 18 -26 0 1 "0.97V" 1>
|
||||
<Lib npn13G1 1 110 270 10 64 0 0 "/home/pedersen/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "npn13G2" 0 "10" 1>
|
||||
<GND * 1 240 430 0 0 0 0>
|
||||
<GND * 1 670 420 0 0 0 0>
|
||||
<Vdc V1 1 670 370 18 -26 0 1 "1.65V" 1>
|
||||
<Lib npn13G2 1 360 270 30 64 1 2 "/home/pedersen/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "npn13G2" 0 "10" 1>
|
||||
<L L21 1 170 400 -26 10 0 0 "300pH" 1 "" 0>
|
||||
<L L25 1 -70 320 -96 -26 0 3 "254.5pH" 1 "" 0>
|
||||
<C C25 1 -150 270 -20 -49 0 2 "36fF" 1 "" 0 "neutral" 0>
|
||||
<C C29 1 -150 480 -20 -49 0 2 "36fF" 1 "" 0 "neutral" 0>
|
||||
<L L29 1 300 400 -26 10 0 0 "300pH" 1 "" 0>
|
||||
<L L30 1 -70 410 -96 -26 0 3 "254.5pH" 1 "" 0>
|
||||
<IProbe Pr1 1 -230 270 -26 16 0 0>
|
||||
<.HB HB1 1 -300 40 0 61 0 0 "50 GHz" 1 "5" 1 "1 pA" 0 "1 uV" 0 "0.001" 0 "150" 0>
|
||||
<C C31 1 570 210 -20 -49 0 2 "10p" 1 "" 0 "neutral" 0>
|
||||
<L L31 1 110 20 -96 -26 0 3 "10n" 1 "" 0>
|
||||
<L L32 1 360 10 -96 -26 0 3 "10n" 1 "" 0>
|
||||
<C C30 1 560 60 -20 -49 0 2 "10p" 1 "" 0 "neutral" 0>
|
||||
<IProbe Pr2 1 640 60 -26 16 0 0>
|
||||
<Pac P4 1 -310 330 18 -26 0 1 "1" 1 "50 Ohm" 1 "-30 dBm" 1 "50e9" 0 "26.85" 0 "true" 0>
|
||||
<SpiceLib SpiceLib1 1 430 -90 -12 16 0 0 "/home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/xyce/models/cornerHBT.lib" 1 "hbt_typ" 1>
|
||||
<Pac P3 1 -310 430 18 -26 0 1 "3" 1 "50 Ohm" 1 "-30 dBm" 1 "50e9" 0 "26.85" 0 "true" 0>
|
||||
<Pac P5 1 710 140 18 -26 0 1 "2" 1 "50 Ohm" 1 "-30 dBm" 1 "50e9" 0 "26.85" 0 "true" 0>
|
||||
<.TR TR1 1 -300 -120 0 61 0 0 "lin" 1 "0" 1 "200 ps" 1 "200" 0 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0>
|
||||
<GND * 1 -340 380 0 0 0 3>
|
||||
</Components>
|
||||
<Wires>
|
||||
<110 320 110 400 "VE" 50 300 27 "">
|
||||
<570 400 570 420 "" 0 0 0 "">
|
||||
<570 310 570 340 "" 0 0 0 "">
|
||||
<-120 270 -70 270 "" 0 0 0 "">
|
||||
<-120 480 -70 480 "" 0 0 0 "">
|
||||
<-70 270 80 270 "Vbase" 30 220 111 "">
|
||||
<110 400 140 400 "" 0 0 0 "">
|
||||
<240 400 240 430 "" 0 0 0 "">
|
||||
<200 400 240 400 "" 0 0 0 "">
|
||||
<240 400 270 400 "" 0 0 0 "">
|
||||
<670 400 670 420 "" 0 0 0 "">
|
||||
<670 310 670 340 "" 0 0 0 "">
|
||||
<120 270 240 270 "" 0 0 0 "">
|
||||
<240 270 240 400 "" 0 0 0 "">
|
||||
<-70 440 -70 480 "" 0 0 0 "">
|
||||
<240 270 350 270 "" 0 0 0 "">
|
||||
<330 400 360 400 "" 0 0 0 "">
|
||||
<360 320 360 400 "" 0 0 0 "">
|
||||
<-70 480 390 480 "" 0 0 0 "">
|
||||
<390 270 390 480 "" 0 0 0 "">
|
||||
<-70 350 -70 380 "Vb" -120 340 14 "">
|
||||
<-70 270 -70 290 "" 0 0 0 "">
|
||||
<-200 270 -180 270 "" 0 0 0 "">
|
||||
<-310 270 -260 270 "" 0 0 0 "">
|
||||
<-310 270 -310 300 "" 0 0 0 "">
|
||||
<360 210 360 220 "" 0 0 0 "">
|
||||
<360 210 540 210 "" 0 0 0 "">
|
||||
<360 40 360 210 "" 0 0 0 "">
|
||||
<240 -100 240 -80 "" 0 0 0 "">
|
||||
<240 -80 360 -80 "" 0 0 0 "">
|
||||
<360 -80 360 -20 "" 0 0 0 "">
|
||||
<110 -80 240 -80 "" 0 0 0 "">
|
||||
<110 -80 110 -10 "" 0 0 0 "">
|
||||
<110 50 110 60 "" 0 0 0 "">
|
||||
<110 60 110 220 "Collector_voltage" 140 170 141 "">
|
||||
<110 60 530 60 "" 0 0 0 "">
|
||||
<590 60 610 60 "" 0 0 0 "">
|
||||
<670 60 710 60 "Vout_p" 730 30 33 "">
|
||||
<710 60 710 110 "" 0 0 0 "">
|
||||
<600 210 710 210 "" 0 0 0 "">
|
||||
<710 170 710 210 "" 0 0 0 "">
|
||||
<-310 480 -180 480 "" 0 0 0 "">
|
||||
<-310 460 -310 480 "" 0 0 0 "">
|
||||
<-310 360 -310 380 "" 0 0 0 "">
|
||||
<-310 380 -310 400 "" 0 0 0 "">
|
||||
<-340 380 -310 380 "" 0 0 0 "">
|
||||
<570 310 570 310 "Vb" 600 280 0 "">
|
||||
<670 310 670 310 "Vcc" 700 280 0 "">
|
||||
<-310 270 -310 270 "Vin_p" -370 230 0 "">
|
||||
<240 -100 240 -100 "Vcc" 270 -130 0 "">
|
||||
</Wires>
|
||||
<Diagrams>
|
||||
<Rect 650 720 240 160 3 #c0c0c0 1 00 1 -2.5e+11 1e+11 2.5e+11 1 -0.0159718 0.1 0.2 0 -0.000313269 0.002 0.005 315 0 225 1 0 0 "" "" "">
|
||||
<"xyce/I(PR1)" #0000ff 0 3 0 6 1>
|
||||
<Mkr -5e+10 -14 -228 3 1 0>
|
||||
<"xyce/V(VIN_P)" #ff0000 0 3 0 6 0>
|
||||
<Mkr 5e+10 184 -230 3 1 0>
|
||||
</Rect>
|
||||
<Rect 1090 720 240 160 3 #c0c0c0 1 00 1 -2.5e+11 1e+11 2.5e+11 1 -0.00233409 0.01 0.025675 0 -0.000313269 0.002 0.005 315 0 225 1 0 0 "" "" "">
|
||||
<"xyce/V(VOUT_P)" #0000ff 0 3 0 6 0>
|
||||
<Mkr 5e+10 204 -207 3 2 0>
|
||||
<"xyce/I(PR2)" #ff0000 0 3 0 6 0>
|
||||
<Mkr -5e+10 156 -76 3 2 0>
|
||||
</Rect>
|
||||
<Rect -310 726 810 146 3 #c0c0c0 1 00 0 0 1e-11 2e-10 1 -0.177311 1 2 1 -1 1 1 315 0 225 1 0 0 "" "" "">
|
||||
<"xyce/tran.V(VIN_P)" #0000ff 0 3 0 0 0>
|
||||
</Rect>
|
||||
<Rect -310 896 810 146 3 #c0c0c0 1 00 0 0 1e-11 2e-10 1 -0.01307 0.02 0.02 1 -1 1 1 315 0 225 1 0 0 "" "" "">
|
||||
<"xyce/tran.V(VOUT_P)" #0000ff 0 3 0 0 0>
|
||||
</Rect>
|
||||
</Diagrams>
|
||||
<Paintings>
|
||||
</Paintings>
|
||||
|
|
@ -0,0 +1,252 @@
|
|||
v {xschem version=3.4.5 file_version=1.2
|
||||
}
|
||||
G {}
|
||||
K {}
|
||||
V {}
|
||||
S {}
|
||||
E {}
|
||||
N 490 -650 490 -600 {
|
||||
lab=#net1}
|
||||
N 810 -650 810 -600 {
|
||||
lab=#net1}
|
||||
N 550 -830 610 -830 {
|
||||
lab=vbias}
|
||||
N 650 -930 1060 -930 {
|
||||
lab=vdd}
|
||||
N 650 -800 650 -770 {
|
||||
lab=#net2}
|
||||
N 1060 -470 1060 -450 {
|
||||
lab=out-}
|
||||
N 980 -530 1020 -530 {
|
||||
lab=#net3}
|
||||
N 980 -470 980 -420 {
|
||||
lab=#net3}
|
||||
N 980 -420 1020 -420 {
|
||||
lab=#net3}
|
||||
N 1060 -930 1060 -530 {
|
||||
lab=vdd}
|
||||
N 810 -540 810 -470 {
|
||||
lab=#net3}
|
||||
N 810 -470 980 -470 {
|
||||
lab=#net3}
|
||||
N 980 -530 980 -470 {
|
||||
lab=#net3}
|
||||
N 720 -270 720 -230 {
|
||||
lab=#net3}
|
||||
N 810 -270 900 -270 {
|
||||
lab=#net3}
|
||||
N 900 -270 900 -230 {
|
||||
lab=#net3}
|
||||
N 810 -470 810 -270 {
|
||||
lab=#net3}
|
||||
N 720 -270 810 -270 {
|
||||
lab=#net3}
|
||||
N 810 -130 900 -130 {
|
||||
lab=gnd}
|
||||
N 900 -170 900 -130 {
|
||||
lab=gnd}
|
||||
N 720 -170 720 -130 {
|
||||
lab=gnd}
|
||||
N 810 -200 900 -200 {
|
||||
lab=gnd}
|
||||
N 400 -270 400 -230 {
|
||||
lab=#net4}
|
||||
N 490 -270 580 -270 {
|
||||
lab=#net4}
|
||||
N 580 -270 580 -230 {
|
||||
lab=#net4}
|
||||
N 400 -270 490 -270 {
|
||||
lab=#net4}
|
||||
N 490 -130 580 -130 {
|
||||
lab=gnd}
|
||||
N 580 -170 580 -130 {
|
||||
lab=gnd}
|
||||
N 400 -170 400 -130 {
|
||||
lab=gnd}
|
||||
N 490 -200 580 -200 {
|
||||
lab=gnd}
|
||||
N 650 -650 810 -650 {
|
||||
lab=#net1}
|
||||
N 650 -710 650 -650 {
|
||||
lab=#net1}
|
||||
N 490 -650 650 -650 {
|
||||
lab=#net1}
|
||||
N 650 -930 650 -830 {
|
||||
lab=vdd}
|
||||
N 650 -740 700 -740 {
|
||||
lab=vdd}
|
||||
N 490 -570 810 -570 {
|
||||
lab=vdd}
|
||||
N 320 -470 490 -470 {
|
||||
lab=#net4}
|
||||
N 490 -470 490 -270 {
|
||||
lab=#net4}
|
||||
N 490 -540 490 -470 {
|
||||
lab=#net4}
|
||||
N 240 -470 240 -450 {
|
||||
lab=out+}
|
||||
N 280 -530 320 -530 {
|
||||
lab=#net4}
|
||||
N 320 -470 320 -420 {
|
||||
lab=#net4}
|
||||
N 280 -420 320 -420 {
|
||||
lab=#net4}
|
||||
N 320 -530 320 -470 {
|
||||
lab=#net4}
|
||||
N 240 -930 240 -530 {
|
||||
lab=vdd}
|
||||
N 240 -930 650 -930 {
|
||||
lab=vdd}
|
||||
N 240 -130 400 -130 {
|
||||
lab=gnd}
|
||||
N 580 -130 720 -130 {
|
||||
lab=gnd}
|
||||
N 900 -130 1060 -130 {
|
||||
lab=gnd}
|
||||
N 490 -470 680 -200 {
|
||||
lab=#net4}
|
||||
N 620 -200 810 -470 {
|
||||
lab=#net3}
|
||||
N 140 -470 240 -470 {
|
||||
lab=out+}
|
||||
N 240 -500 240 -470 {
|
||||
lab=out+}
|
||||
N 1060 -470 1160 -470 {
|
||||
lab=out-}
|
||||
N 1060 -500 1060 -470 {
|
||||
lab=out-}
|
||||
N 330 -200 360 -200 {
|
||||
lab=clk}
|
||||
N 440 -570 450 -570 {
|
||||
lab=v+}
|
||||
N 850 -570 860 -570 {
|
||||
lab=v-}
|
||||
N 360 -740 610 -740 {
|
||||
lab=clk}
|
||||
N 360 -740 360 -200 {
|
||||
lab=clk}
|
||||
N 1060 -420 1060 -130 {
|
||||
lab=gnd}
|
||||
N 810 -200 810 -130 {
|
||||
lab=gnd}
|
||||
N 720 -200 810 -200 {
|
||||
lab=gnd}
|
||||
N 720 -130 810 -130 {
|
||||
lab=gnd}
|
||||
N 490 -200 490 -130 {
|
||||
lab=gnd}
|
||||
N 400 -200 490 -200 {
|
||||
lab=gnd}
|
||||
N 400 -130 490 -130 {
|
||||
lab=gnd}
|
||||
N 240 -420 240 -130 {
|
||||
lab=gnd}
|
||||
N 940 -200 960 -200 {
|
||||
lab=clk}
|
||||
C {iopin.sym} 1060 -930 0 0 {name=p1 lab=vdd}
|
||||
C {iopin.sym} 1060 -130 0 0 {name=p2 lab=gnd}
|
||||
C {ipin.sym} 440 -570 0 0 {name=p3 lab=v+}
|
||||
C {ipin.sym} 860 -570 0 1 {name=p4 lab=v-}
|
||||
C {ipin.sym} 550 -830 0 0 {name=p5 lab=vbias}
|
||||
C {ipin.sym} 330 -200 0 0 {name=p6 lab=clk}
|
||||
C {opin.sym} 1160 -470 0 0 {name=p7 lab=out-}
|
||||
C {opin.sym} 140 -470 0 1 {name=p8 lab=out+}
|
||||
C {lab_pin.sym} 650 -570 3 0 {name=p9 sig_type=std_logic lab=vdd}
|
||||
C {lab_pin.sym} 700 -740 2 0 {name=p10 sig_type=std_logic lab=vdd}
|
||||
C {sg13g2_pr/sg13_lv_pmos.sym} 630 -740 0 0 {name=M13
|
||||
l=0.300u
|
||||
w=10u
|
||||
ng=1
|
||||
m=1
|
||||
model=sg13_lv_pmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {sg13g2_pr/sg13_lv_pmos.sym} 630 -830 0 0 {name=M3
|
||||
l=0.300u
|
||||
w=10u
|
||||
ng=1
|
||||
m=1
|
||||
model=sg13_lv_pmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {sg13g2_pr/sg13_lv_pmos.sym} 470 -570 0 0 {name=M2
|
||||
l=0.200u
|
||||
w=5u
|
||||
ng=1
|
||||
m=1
|
||||
model=sg13_lv_pmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {sg13g2_pr/sg13_lv_pmos.sym} 830 -570 0 1 {name=M1
|
||||
l=0.200u
|
||||
w=5u
|
||||
ng=1
|
||||
m=1
|
||||
model=sg13_lv_pmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {sg13g2_pr/sg13_lv_pmos.sym} 1040 -530 0 0 {name=M4
|
||||
l=0.200u
|
||||
w=1u
|
||||
ng=1
|
||||
m=1
|
||||
model=sg13_lv_pmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {sg13g2_pr/sg13_lv_pmos.sym} 260 -530 0 1 {name=M5
|
||||
l=0.200u
|
||||
w=1u
|
||||
ng=1
|
||||
m=1
|
||||
model=sg13_lv_pmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {sg13g2_pr/sg13_lv_nmos.sym} 260 -420 2 0 {name=M11
|
||||
l=0.75u
|
||||
w=1.0u
|
||||
ng=1
|
||||
m=1
|
||||
model=sg13_lv_nmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {sg13g2_pr/sg13_lv_nmos.sym} 1040 -420 2 1 {name=M12
|
||||
l=0.75u
|
||||
w=1.0u
|
||||
ng=1
|
||||
m=1
|
||||
model=sg13_lv_nmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {sg13g2_pr/sg13_lv_nmos.sym} 600 -200 2 0 {name=M6
|
||||
l=0.75u
|
||||
w=1.0u
|
||||
ng=1
|
||||
m=1
|
||||
model=sg13_lv_nmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {sg13g2_pr/sg13_lv_nmos.sym} 380 -200 2 1 {name=M10
|
||||
l=0.75u
|
||||
w=1.0u
|
||||
ng=1
|
||||
m=1
|
||||
model=sg13_lv_nmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {sg13g2_pr/sg13_lv_nmos.sym} 920 -200 2 0 {name=M7
|
||||
l=0.75u
|
||||
w=1.0u
|
||||
ng=1
|
||||
m=1
|
||||
model=sg13_lv_nmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {sg13g2_pr/sg13_lv_nmos.sym} 700 -200 2 1 {name=M8
|
||||
l=0.75u
|
||||
w=1.0u
|
||||
ng=1
|
||||
m=1
|
||||
model=sg13_lv_nmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {lab_pin.sym} 960 -200 2 0 {name=p11 sig_type=std_logic lab=clk}
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
v {xschem version=3.4.5 file_version=1.2
|
||||
}
|
||||
G {}
|
||||
K {type=subcircuit
|
||||
format="@name @pinlist @symname"
|
||||
template="name=x1"
|
||||
}
|
||||
V {}
|
||||
S {}
|
||||
E {}
|
||||
L 4 -130 -100 130 0 {}
|
||||
L 4 -130 100 130 0 {}
|
||||
L 4 -130 -100 -130 100 {}
|
||||
L 4 -150 0 -130 0 {}
|
||||
L 4 -150 -60 -130 -60 {}
|
||||
L 4 -150 60 -130 60 {}
|
||||
L 4 110 10 130 10 {}
|
||||
L 4 110 -10 130 -10 {}
|
||||
L 4 -20 60 -20 80 {}
|
||||
L 7 -70 -100 -70 -80 {}
|
||||
L 7 -70 80 -70 100 {}
|
||||
B 5 -72.5 -102.5 -67.5 -97.5 {name=vdd dir=inout}
|
||||
B 5 -152.5 -2.5 -147.5 2.5 {name=vbias dir=in}
|
||||
B 5 -152.5 -62.5 -147.5 -57.5 {name=v+ dir=in}
|
||||
B 5 -152.5 57.5 -147.5 62.5 {name=v- dir=in}
|
||||
B 5 127.5 7.5 132.5 12.5 {name=out- dir=out}
|
||||
B 5 127.5 -12.5 132.5 -7.5 {name=out+ dir=out}
|
||||
B 5 -22.5 77.5 -17.5 82.5 {name=clk dir=in}
|
||||
B 5 -72.5 97.5 -67.5 102.5 {name=gnd dir=inout}
|
||||
T {@symname} -89 -6 0 0 0.3 0.3 {}
|
||||
T {@name} 25 -52 0 0 0.2 0.2 {}
|
||||
T {vdd} -74 -75 3 1 0.2 0.2 {}
|
||||
T {vbias} -125 -4 0 0 0.2 0.2 {}
|
||||
T {v+} -125 -64 0 0 0.2 0.2 {}
|
||||
T {v-} -125 56 0 0 0.2 0.2 {}
|
||||
T {out-} 90 1 0 1 0.2 0.2 {}
|
||||
T {out+} 95 -14 0 1 0.2 0.2 {}
|
||||
T {clk} -24 55 3 0 0.2 0.2 {}
|
||||
T {gnd} -66 75 1 1 0.2 0.2 {}
|
||||
|
|
@ -0,0 +1,167 @@
|
|||
v {xschem version=3.4.5 file_version=1.2
|
||||
}
|
||||
G {}
|
||||
K {}
|
||||
V {}
|
||||
S {}
|
||||
E {}
|
||||
B 2 330 -910 1130 -510 {flags=graph
|
||||
y1=0
|
||||
y2=2
|
||||
ypos1=0
|
||||
ypos2=2
|
||||
divy=5
|
||||
subdivy=1
|
||||
unity=1
|
||||
x1=0
|
||||
x2=10e-6
|
||||
divx=5
|
||||
subdivx=1
|
||||
xlabmag=1.0
|
||||
ylabmag=1.0
|
||||
node=""
|
||||
color=""
|
||||
dataset=-1
|
||||
unitx=1
|
||||
logx=0
|
||||
logy=0
|
||||
}
|
||||
N -540 -180 -540 -160 {
|
||||
lab=vbias}
|
||||
N -610 -180 -610 -160 {
|
||||
lab=vdd}
|
||||
N -610 -100 -610 -80 {
|
||||
lab=GND}
|
||||
N -570 -80 -540 -80 {
|
||||
lab=GND}
|
||||
N -420 -180 -420 -160 {
|
||||
lab=clk}
|
||||
N -420 -100 -420 -70 {
|
||||
lab=GND}
|
||||
N -570 -80 -570 -70 {
|
||||
lab=GND}
|
||||
N -420 -70 -210 -70 {
|
||||
lab=GND}
|
||||
N -210 -100 -210 -70 {
|
||||
lab=GND}
|
||||
N -210 -180 -210 -160 {
|
||||
lab=vip}
|
||||
N 60 -220 120 -220 {
|
||||
lab=vbias}
|
||||
N 200 -120 200 -90 {
|
||||
lab=GND}
|
||||
N 250 -140 250 -110 {
|
||||
lab=clk}
|
||||
N 200 -350 200 -320 {
|
||||
lab=vdd}
|
||||
N 400 -210 500 -210 {
|
||||
lab=outm}
|
||||
N 400 -230 500 -230 {
|
||||
lab=outp}
|
||||
N 80 -160 120 -160 {
|
||||
lab=vbias}
|
||||
N 80 -280 120 -280 {
|
||||
lab=vip}
|
||||
N -610 -80 -570 -80 {
|
||||
lab=GND}
|
||||
N -540 -100 -540 -80 {
|
||||
lab=GND}
|
||||
N 80 -300 80 -280 {
|
||||
lab=vip}
|
||||
N 60 -280 80 -280 {
|
||||
lab=vip}
|
||||
N 80 -160 80 -140 {
|
||||
lab=vbias}
|
||||
N 60 -160 80 -160 {
|
||||
lab=vbias}
|
||||
N 80 -80 80 -60 {
|
||||
lab=GND}
|
||||
N 80 -380 80 -360 {
|
||||
lab=GND}
|
||||
N 460 -150 460 -140 {
|
||||
lab=GND}
|
||||
N 460 -300 460 -290 {
|
||||
lab=GND}
|
||||
C {devices/code_shown.sym} -675 -470 0 0 {name=MODEL only_toplevel=false
|
||||
format="tcleval( @value )"
|
||||
value="
|
||||
.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ
|
||||
.lib cornerMOSlv.lib mos_tt
|
||||
"}
|
||||
C {vsource.sym} -610 -130 0 0 {name=V3 value="DC 1.2"}
|
||||
C {vsource.sym} -540 -130 0 0 {name=V4 value="DC 0.6"}
|
||||
C {gnd.sym} -310 -70 0 0 {name=l1 lab=GND}
|
||||
C {lab_pin.sym} -540 -180 2 0 {name=p3 sig_type=std_logic lab=vbias}
|
||||
C {lab_pin.sym} -610 -180 2 0 {name=p4 sig_type=std_logic lab=vdd}
|
||||
C {vsource.sym} -420 -130 0 0 {name=V1 value="PULSE(0 1.2 0 0 0 5N \{period\})"}
|
||||
C {lab_pin.sym} -420 -180 2 0 {name=p1 sig_type=std_logic lab=clk}
|
||||
C {gnd.sym} -570 -70 0 0 {name=l2 lab=GND}
|
||||
C {vsource.sym} -210 -130 0 0 {name=V2 value="PULSE(595e-3 605e-3 0 tr 1S 1S"}
|
||||
C {lab_pin.sym} -210 -180 2 0 {name=p2 sig_type=std_logic lab=vip}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_1_comparator/schematic/dynamic_comparator.sym} 270 -220 0 0 {name=x1}
|
||||
C {lab_pin.sym} 60 -280 2 1 {name=p5 sig_type=std_logic lab=vip}
|
||||
C {lab_pin.sym} 200 -350 2 0 {name=p6 sig_type=std_logic lab=vdd}
|
||||
C {lab_pin.sym} 60 -220 2 1 {name=p7 sig_type=std_logic lab=vbias}
|
||||
C {lab_pin.sym} 60 -160 2 1 {name=p8 sig_type=std_logic lab=vbias}
|
||||
C {lab_pin.sym} 250 -110 2 0 {name=p9 sig_type=std_logic lab=clk}
|
||||
C {gnd.sym} 200 -90 0 0 {name=l3 lab=GND}
|
||||
C {lab_pin.sym} 500 -230 2 0 {name=p10 sig_type=std_logic lab=outp}
|
||||
C {lab_pin.sym} 500 -210 2 0 {name=p11 sig_type=std_logic lab=outm}
|
||||
C {capa.sym} 80 -110 0 0 {name=C1
|
||||
m=1
|
||||
value=16.384p
|
||||
footprint=1206
|
||||
device="ceramic capacitor"}
|
||||
C {gnd.sym} 80 -60 0 0 {name=l4 lab=GND}
|
||||
C {gnd.sym} 80 -380 2 0 {name=l5 lab=GND}
|
||||
C {capa.sym} 80 -330 2 0 {name=C2
|
||||
m=1
|
||||
value=16.384p
|
||||
footprint=1206
|
||||
device="ceramic capacitor"}
|
||||
C {capa.sym} 460 -260 2 0 {name=C4
|
||||
m=1
|
||||
value=15f
|
||||
footprint=1206
|
||||
device="ceramic capacitor"}
|
||||
C {capa.sym} 460 -180 0 0 {name=C3
|
||||
m=1
|
||||
value=15f
|
||||
footprint=1206
|
||||
device="ceramic capacitor"}
|
||||
C {gnd.sym} 460 -140 0 0 {name=l6 lab=GND}
|
||||
C {gnd.sym} 460 -300 2 0 {name=l7 lab=GND}
|
||||
C {launcher.sym} 170 -630 0 0 {name=h5
|
||||
descr="load waves"
|
||||
tclcommand="xschem raw_read $netlist_dir/output_file.raw tran"
|
||||
}
|
||||
C {devices/code_shown.sym} -735 -1130 0 0 {name=NGSPICE only_toplevel=false
|
||||
value="
|
||||
.control
|
||||
op
|
||||
.param clock = 100e6 ; 100 MHz clock
|
||||
.param period = 1 / clock
|
||||
.param num_cycles = 80 ; number of evaluation cycles
|
||||
.param tr = num_cycles * period
|
||||
tran 300p 800n
|
||||
save all
|
||||
|
||||
; Define vdiff as the output differential voltage
|
||||
let vdiff = v(outp) - v(outm)
|
||||
|
||||
; Measure when vdiff = 0.65V
|
||||
meas tran cross_time WHEN vdiff = 0.65 RISE=1
|
||||
|
||||
; define input differentially also
|
||||
let vindiff = v(vip) - v(vbias)
|
||||
|
||||
; Measure the difference of the input
|
||||
meas tran offset_voltage find vindiff at=cross_time RISE=1
|
||||
let save_offset_voltage = offset_voltage
|
||||
print save_offset_voltage > vbe_tempvar.txt
|
||||
|
||||
|
||||
write output.raw
|
||||
|
||||
.endc
|
||||
"}
|
||||
|
|
@ -0,0 +1,254 @@
|
|||
v {xschem version=3.4.5 file_version=1.2
|
||||
}
|
||||
G {}
|
||||
K {}
|
||||
V {}
|
||||
S {}
|
||||
E {}
|
||||
B 2 20 -1225 820 -825 {flags=graph
|
||||
y1=0.046228722
|
||||
y2=1.0862287
|
||||
ypos1=0
|
||||
ypos2=2
|
||||
divy=5
|
||||
subdivy=1
|
||||
unity=1
|
||||
x1=0
|
||||
|
||||
divx=5
|
||||
subdivx=4
|
||||
xlabmag=1.0
|
||||
ylabmag=1.0
|
||||
|
||||
|
||||
dataset=-1
|
||||
unitx=1
|
||||
logx=0
|
||||
logy=0
|
||||
x2=1e-06
|
||||
color=4
|
||||
node=clk}
|
||||
B 2 20 -805 820 -405 {flags=graph
|
||||
y1=0.59
|
||||
y2=0.61
|
||||
ypos1=0
|
||||
ypos2=2
|
||||
divy=5
|
||||
subdivy=1
|
||||
unity=1
|
||||
x1=0
|
||||
|
||||
divx=5
|
||||
subdivx=4
|
||||
xlabmag=1.0
|
||||
ylabmag=1.0
|
||||
|
||||
|
||||
dataset=-1
|
||||
unitx=1
|
||||
logx=0
|
||||
logy=0
|
||||
x2=1e-06
|
||||
|
||||
|
||||
color=4
|
||||
node=v+}
|
||||
B 2 850 -1225 1650 -825 {flags=graph
|
||||
y1=-1.3
|
||||
y2=1.3
|
||||
ypos1=0
|
||||
ypos2=2
|
||||
divy=5
|
||||
subdivy=1
|
||||
unity=1
|
||||
x1=0
|
||||
|
||||
divx=5
|
||||
subdivx=4
|
||||
xlabmag=1.0
|
||||
ylabmag=1.0
|
||||
|
||||
|
||||
dataset=-1
|
||||
unitx=1
|
||||
logx=0
|
||||
logy=0
|
||||
x2=1e-06
|
||||
|
||||
|
||||
color=4
|
||||
node=vout}
|
||||
B 2 850 -805 1650 -405 {flags=graph
|
||||
y1=-0.7005027
|
||||
y2=1.1959773
|
||||
ypos1=0
|
||||
ypos2=2
|
||||
divy=5
|
||||
subdivy=1
|
||||
unity=1
|
||||
x1=0
|
||||
|
||||
divx=5
|
||||
subdivx=4
|
||||
xlabmag=1.0
|
||||
ylabmag=1.0
|
||||
|
||||
|
||||
dataset=-1
|
||||
unitx=1
|
||||
logx=0
|
||||
logy=0
|
||||
x2=1e-06
|
||||
|
||||
color=4
|
||||
node=outp}
|
||||
B 2 850 -395 1650 5 {flags=graph
|
||||
y1=0.24502661
|
||||
y2=1.4615386
|
||||
ypos1=0
|
||||
ypos2=2
|
||||
divy=5
|
||||
subdivy=1
|
||||
unity=1
|
||||
x1=0
|
||||
|
||||
divx=5
|
||||
subdivx=4
|
||||
xlabmag=1.0
|
||||
ylabmag=1.0
|
||||
|
||||
|
||||
dataset=-1
|
||||
unitx=1
|
||||
logx=0
|
||||
logy=0
|
||||
x2=1e-06
|
||||
|
||||
|
||||
color=4
|
||||
node=outm}
|
||||
N -540 -180 -540 -160 {
|
||||
lab=vbias}
|
||||
N -610 -180 -610 -160 {
|
||||
lab=vdd}
|
||||
N -610 -100 -610 -80 {
|
||||
lab=GND}
|
||||
N -570 -80 -540 -80 {
|
||||
lab=GND}
|
||||
N -420 -180 -420 -160 {
|
||||
lab=clk}
|
||||
N -420 -100 -420 -70 {
|
||||
lab=GND}
|
||||
N -570 -80 -570 -70 {
|
||||
lab=GND}
|
||||
N -420 -70 -210 -70 {
|
||||
lab=GND}
|
||||
N -210 -100 -210 -70 {
|
||||
lab=GND}
|
||||
N -210 -180 -210 -160 {
|
||||
lab=vinp}
|
||||
N 60 -220 120 -220 {
|
||||
lab=vbias}
|
||||
N 200 -120 200 -90 {
|
||||
lab=GND}
|
||||
N 250 -140 250 -110 {
|
||||
lab=clk}
|
||||
N 200 -350 200 -320 {
|
||||
lab=vdd}
|
||||
N 400 -210 500 -210 {
|
||||
lab=outm}
|
||||
N 400 -230 500 -230 {
|
||||
lab=outp}
|
||||
N 80 -160 120 -160 {
|
||||
lab=vbias}
|
||||
N 80 -280 120 -280 {
|
||||
lab=vinp}
|
||||
N -610 -80 -570 -80 {
|
||||
lab=GND}
|
||||
N -540 -100 -540 -80 {
|
||||
lab=GND}
|
||||
N 80 -300 80 -280 {
|
||||
lab=vinp}
|
||||
N 60 -280 80 -280 {
|
||||
lab=vinp}
|
||||
N 80 -160 80 -140 {
|
||||
lab=vbias}
|
||||
N 60 -160 80 -160 {
|
||||
lab=vbias}
|
||||
N 80 -80 80 -60 {
|
||||
lab=GND}
|
||||
N 80 -380 80 -360 {
|
||||
lab=GND}
|
||||
N 460 -150 460 -140 {
|
||||
lab=GND}
|
||||
N 460 -300 460 -290 {
|
||||
lab=GND}
|
||||
C {devices/code_shown.sym} -675 -490 0 0 {name=MODEL only_toplevel=false
|
||||
format="tcleval( @value )"
|
||||
value="
|
||||
.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ
|
||||
.lib cornerMOSlv.lib mos_tt
|
||||
"}
|
||||
C {devices/code_shown.sym} -685 -780 0 0 {name=NGSPICE only_toplevel=false
|
||||
value="
|
||||
.control
|
||||
op
|
||||
.param clock = 100e6 ; 100 MHz clock
|
||||
.param period = 1 / clock
|
||||
.param num_cycles = 100 ; number of evaluation cycles
|
||||
.param tr = num_cycles * period
|
||||
tran 500p 1u
|
||||
.save all
|
||||
let vindiff = (v(vinp))-(v(vbias))
|
||||
let clk = v(clk)
|
||||
let vout = (v(outp))-(v(outm))
|
||||
write output_file.raw
|
||||
.endc
|
||||
"}
|
||||
C {launcher.sym} -160 -855 0 0 {name=h5
|
||||
descr="load waves"
|
||||
tclcommand="xschem raw_read $netlist_dir/output_file.raw tran"
|
||||
}
|
||||
C {vsource.sym} -610 -130 0 0 {name=V3 value="DC 1.2"}
|
||||
C {vsource.sym} -540 -130 0 0 {name=V4 value="DC 0.6"}
|
||||
C {gnd.sym} -310 -70 0 0 {name=l1 lab=GND}
|
||||
C {lab_pin.sym} -540 -180 2 0 {name=p3 sig_type=std_logic lab=vbias}
|
||||
C {lab_pin.sym} -610 -180 2 0 {name=p4 sig_type=std_logic lab=vdd}
|
||||
C {vsource.sym} -420 -130 0 0 {name=V1 value="PULSE(0 1.2 0 0 0 5N \{period\})"}
|
||||
C {lab_pin.sym} -420 -180 2 0 {name=p1 sig_type=std_logic lab=clk}
|
||||
C {gnd.sym} -570 -70 0 0 {name=l2 lab=GND}
|
||||
C {vsource.sym} -210 -130 0 0 {name=V2 value="PULSE(595e-3 605e-3 0 tr 1S 1S)"}
|
||||
C {lab_pin.sym} -210 -180 2 0 {name=p2 sig_type=std_logic lab=vinp}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_1_comparator/schematic/dynamic_comparator.sym} 270 -220 0 0 {name=x1}
|
||||
C {lab_pin.sym} 60 -280 2 1 {name=p5 sig_type=std_logic lab=vinp}
|
||||
C {lab_pin.sym} 200 -350 2 0 {name=p6 sig_type=std_logic lab=vdd}
|
||||
C {lab_pin.sym} 60 -220 2 1 {name=p7 sig_type=std_logic lab=vbias}
|
||||
C {lab_pin.sym} 60 -160 2 1 {name=p8 sig_type=std_logic lab=vbias}
|
||||
C {lab_pin.sym} 250 -110 2 0 {name=p9 sig_type=std_logic lab=clk}
|
||||
C {gnd.sym} 200 -90 0 0 {name=l3 lab=GND}
|
||||
C {lab_pin.sym} 500 -230 2 0 {name=p10 sig_type=std_logic lab=outp}
|
||||
C {lab_pin.sym} 500 -210 2 0 {name=p11 sig_type=std_logic lab=outm}
|
||||
C {capa.sym} 80 -110 0 0 {name=C1
|
||||
m=1
|
||||
value=16.384p
|
||||
footprint=1206
|
||||
device="ceramic capacitor"}
|
||||
C {gnd.sym} 80 -60 0 0 {name=l4 lab=GND}
|
||||
C {gnd.sym} 80 -380 2 0 {name=l5 lab=GND}
|
||||
C {capa.sym} 80 -330 2 0 {name=C2
|
||||
m=1
|
||||
value=16.384p
|
||||
footprint=1206
|
||||
device="ceramic capacitor"}
|
||||
C {capa.sym} 460 -260 2 0 {name=C4
|
||||
m=1
|
||||
value=15f
|
||||
footprint=1206
|
||||
device="ceramic capacitor"}
|
||||
C {capa.sym} 460 -180 0 0 {name=C3
|
||||
m=1
|
||||
value=15f
|
||||
footprint=1206
|
||||
device="ceramic capacitor"}
|
||||
C {gnd.sym} 460 -140 0 0 {name=l6 lab=GND}
|
||||
C {gnd.sym} 460 -300 2 0 {name=l7 lab=GND}
|
||||
|
|
@ -0,0 +1,137 @@
|
|||
v {xschem version=3.4.5 file_version=1.2
|
||||
}
|
||||
G {}
|
||||
K {}
|
||||
V {}
|
||||
S {}
|
||||
E {}
|
||||
N -540 -180 -540 -160 {
|
||||
lab=vbias}
|
||||
N -610 -180 -610 -160 {
|
||||
lab=vdd}
|
||||
N -610 -100 -610 -80 {
|
||||
lab=GND}
|
||||
N -570 -80 -540 -80 {
|
||||
lab=GND}
|
||||
N -420 -180 -420 -160 {
|
||||
lab=clk}
|
||||
N -420 -100 -420 -70 {
|
||||
lab=GND}
|
||||
N -570 -80 -570 -70 {
|
||||
lab=GND}
|
||||
N -420 -70 -210 -70 {
|
||||
lab=GND}
|
||||
N -210 -100 -210 -70 {
|
||||
lab=GND}
|
||||
N -210 -180 -210 -160 {
|
||||
lab=vip}
|
||||
N 60 -220 120 -220 {
|
||||
lab=vbias}
|
||||
N 200 -120 200 -90 {
|
||||
lab=GND}
|
||||
N 250 -140 250 -110 {
|
||||
lab=clk}
|
||||
N 200 -350 200 -320 {
|
||||
lab=vdd}
|
||||
N 400 -210 500 -210 {
|
||||
lab=outm}
|
||||
N 400 -230 500 -230 {
|
||||
lab=outp}
|
||||
N 80 -160 120 -160 {
|
||||
lab=vbias}
|
||||
N 80 -280 120 -280 {
|
||||
lab=vip}
|
||||
N -610 -80 -570 -80 {
|
||||
lab=GND}
|
||||
N -540 -100 -540 -80 {
|
||||
lab=GND}
|
||||
N 80 -300 80 -280 {
|
||||
lab=vip}
|
||||
N 60 -280 80 -280 {
|
||||
lab=vip}
|
||||
N 80 -160 80 -140 {
|
||||
lab=vbias}
|
||||
N 60 -160 80 -160 {
|
||||
lab=vbias}
|
||||
N 80 -80 80 -60 {
|
||||
lab=GND}
|
||||
N 80 -380 80 -360 {
|
||||
lab=GND}
|
||||
N 460 -150 460 -140 {
|
||||
lab=GND}
|
||||
N 460 -300 460 -290 {
|
||||
lab=GND}
|
||||
C {devices/code_shown.sym} -685 -530 0 0 {name=MODEL only_toplevel=false
|
||||
format="tcleval( @value )"
|
||||
value="
|
||||
.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ
|
||||
.lib cornerMOSlv.lib mos_tt
|
||||
"}
|
||||
C {vsource.sym} -610 -130 0 0 {name=V3 value="DC 1.2"}
|
||||
C {vsource.sym} -540 -130 0 0 {name=V4 value="DC 0.6"}
|
||||
C {gnd.sym} -310 -70 0 0 {name=l1 lab=GND}
|
||||
C {lab_pin.sym} -540 -180 2 0 {name=p3 sig_type=std_logic lab=vbias}
|
||||
C {lab_pin.sym} -610 -180 2 0 {name=p4 sig_type=std_logic lab=vdd}
|
||||
C {vsource.sym} -420 -130 0 0 {name=V1 value="PULSE(0 1.2 0 0 0 5N \{period\})"}
|
||||
C {lab_pin.sym} -420 -180 2 0 {name=p1 sig_type=std_logic lab=clk}
|
||||
C {gnd.sym} -570 -70 0 0 {name=l2 lab=GND}
|
||||
C {vsource.sym} -210 -130 0 0 {name=V2 value="PULSE(595e-3 605e-3 0 tr 1S 1S"}
|
||||
C {lab_pin.sym} -210 -180 2 0 {name=p2 sig_type=std_logic lab=vip}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_1_comparator/schematic/dynamic_comparator.sym} 270 -220 0 0 {name=x1}
|
||||
C {lab_pin.sym} 60 -280 2 1 {name=p5 sig_type=std_logic lab=vip}
|
||||
C {lab_pin.sym} 200 -350 2 0 {name=p6 sig_type=std_logic lab=vdd}
|
||||
C {lab_pin.sym} 60 -220 2 1 {name=p7 sig_type=std_logic lab=vbias}
|
||||
C {lab_pin.sym} 60 -160 2 1 {name=p8 sig_type=std_logic lab=vbias}
|
||||
C {lab_pin.sym} 250 -110 2 0 {name=p9 sig_type=std_logic lab=clk}
|
||||
C {gnd.sym} 200 -90 0 0 {name=l3 lab=GND}
|
||||
C {lab_pin.sym} 500 -230 2 0 {name=p10 sig_type=std_logic lab=outp}
|
||||
C {lab_pin.sym} 500 -210 2 0 {name=p11 sig_type=std_logic lab=outm}
|
||||
C {capa.sym} 80 -110 0 0 {name=C1
|
||||
m=1
|
||||
value=16.384p
|
||||
footprint=1206
|
||||
device="ceramic capacitor"}
|
||||
C {gnd.sym} 80 -60 0 0 {name=l4 lab=GND}
|
||||
C {gnd.sym} 80 -380 2 0 {name=l5 lab=GND}
|
||||
C {capa.sym} 80 -330 2 0 {name=C2
|
||||
m=1
|
||||
value=16.384p
|
||||
footprint=1206
|
||||
device="ceramic capacitor"}
|
||||
C {capa.sym} 460 -260 2 0 {name=C4
|
||||
m=1
|
||||
value=15f
|
||||
footprint=1206
|
||||
device="ceramic capacitor"}
|
||||
C {capa.sym} 460 -180 0 0 {name=C3
|
||||
m=1
|
||||
value=15f
|
||||
footprint=1206
|
||||
device="ceramic capacitor"}
|
||||
C {gnd.sym} 460 -140 0 0 {name=l6 lab=GND}
|
||||
C {gnd.sym} 460 -300 2 0 {name=l7 lab=GND}
|
||||
C {devices/code_shown.sym} -705 -1010 0 0 {name=NGSPICE only_toplevel=false
|
||||
value="
|
||||
.control
|
||||
let run = 1
|
||||
let mc_runs = 10
|
||||
let results = unitvec(mc_runs)
|
||||
dowhile run <= mc_runs
|
||||
reset
|
||||
.param clock = 100e6 ; 100 MHz clock
|
||||
.param period = 1 / clock
|
||||
.param num_cycles = 80 ; number of evaluation cycles
|
||||
.param tr = num_cycles * period
|
||||
tran 300p 800n
|
||||
set run = $&run
|
||||
let vdiff = v(outp) - v(outm)
|
||||
meas tran cross_time WHEN vdiff = 0.65 RISE=1
|
||||
let vindiff = v(vip) - v(vbias)
|
||||
meas tran offset_voltage_\{$run\} find vindiff at=cross_time RISE=1
|
||||
let results[$run - 1] = offset_voltage_\{$run\}
|
||||
let run = run + 1
|
||||
end
|
||||
print results > vbe_tempvar.txt
|
||||
.endc
|
||||
|
||||
"}
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
v {xschem version=3.4.5 file_version=1.2
|
||||
}
|
||||
G {}
|
||||
K {}
|
||||
V {}
|
||||
S {}
|
||||
E {}
|
||||
N -540 -180 -540 -160 {
|
||||
lab=vbias}
|
||||
N -610 -180 -610 -160 {
|
||||
lab=vdd}
|
||||
N -610 -100 -610 -80 {
|
||||
lab=GND}
|
||||
N -570 -80 -540 -80 {
|
||||
lab=GND}
|
||||
N -420 -180 -420 -160 {
|
||||
lab=clk}
|
||||
N -420 -100 -420 -70 {
|
||||
lab=GND}
|
||||
N -570 -80 -570 -70 {
|
||||
lab=GND}
|
||||
N -420 -70 -210 -70 {
|
||||
lab=GND}
|
||||
N -210 -100 -210 -70 {
|
||||
lab=GND}
|
||||
N -210 -180 -210 -160 {
|
||||
lab=vinp}
|
||||
N 60 -220 120 -220 {
|
||||
lab=vbias}
|
||||
N 200 -120 200 -90 {
|
||||
lab=GND}
|
||||
N 250 -140 250 -110 {
|
||||
lab=clk}
|
||||
N 200 -350 200 -320 {
|
||||
lab=vdd}
|
||||
N 400 -210 500 -210 {
|
||||
lab=outm}
|
||||
N 400 -230 500 -230 {
|
||||
lab=outp}
|
||||
N 80 -160 120 -160 {
|
||||
lab=vbias}
|
||||
N 80 -280 120 -280 {
|
||||
lab=vinp}
|
||||
N -610 -80 -570 -80 {
|
||||
lab=GND}
|
||||
N -540 -100 -540 -80 {
|
||||
lab=GND}
|
||||
N 80 -300 80 -280 {
|
||||
lab=vinp}
|
||||
N 60 -280 80 -280 {
|
||||
lab=vinp}
|
||||
N 80 -160 80 -140 {
|
||||
lab=vbias}
|
||||
N 60 -160 80 -160 {
|
||||
lab=vbias}
|
||||
N 80 -80 80 -60 {
|
||||
lab=GND}
|
||||
N 80 -380 80 -360 {
|
||||
lab=GND}
|
||||
N 460 -150 460 -140 {
|
||||
lab=GND}
|
||||
N 460 -300 460 -290 {
|
||||
lab=GND}
|
||||
C {vsource.sym} -610 -130 0 0 {name=V3 value="DC 1.2"}
|
||||
C {vsource.sym} -540 -130 0 0 {name=V4 value="DC 0.6"}
|
||||
C {gnd.sym} -310 -70 0 0 {name=l1 lab=GND}
|
||||
C {lab_pin.sym} -540 -180 2 0 {name=p3 sig_type=std_logic lab=vbias}
|
||||
C {lab_pin.sym} -610 -180 2 0 {name=p4 sig_type=std_logic lab=vdd}
|
||||
C {vsource.sym} -420 -130 0 0 {name=V1 value="PULSE(0 1.2 0 0 0 5N \{period\})"}
|
||||
C {lab_pin.sym} -420 -180 2 0 {name=p1 sig_type=std_logic lab=clk}
|
||||
C {gnd.sym} -570 -70 0 0 {name=l2 lab=GND}
|
||||
C {vsource.sym} -210 -130 0 0 {name=V2 value="PULSE(595e-3 605e-3 0 tr 1S 1S)"}
|
||||
C {lab_pin.sym} -210 -180 2 0 {name=p2 sig_type=std_logic lab=vinp}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_1_comparator/schematic/dynamic_comparator.sym} 270 -220 0 0 {name=x1}
|
||||
C {lab_pin.sym} 60 -280 2 1 {name=p5 sig_type=std_logic lab=vinp}
|
||||
C {lab_pin.sym} 200 -350 2 0 {name=p6 sig_type=std_logic lab=vdd}
|
||||
C {lab_pin.sym} 60 -220 2 1 {name=p7 sig_type=std_logic lab=vbias}
|
||||
C {lab_pin.sym} 60 -160 2 1 {name=p8 sig_type=std_logic lab=vbias}
|
||||
C {lab_pin.sym} 250 -110 2 0 {name=p9 sig_type=std_logic lab=clk}
|
||||
C {gnd.sym} 200 -90 0 0 {name=l3 lab=GND}
|
||||
C {lab_pin.sym} 500 -230 2 0 {name=p10 sig_type=std_logic lab=outp}
|
||||
C {lab_pin.sym} 500 -210 2 0 {name=p11 sig_type=std_logic lab=outm}
|
||||
C {capa.sym} 80 -110 0 0 {name=C1
|
||||
m=1
|
||||
value=16.384p
|
||||
footprint=1206
|
||||
device="ceramic capacitor"}
|
||||
C {gnd.sym} 80 -60 0 0 {name=l4 lab=GND}
|
||||
C {gnd.sym} 80 -380 2 0 {name=l5 lab=GND}
|
||||
C {capa.sym} 80 -330 2 0 {name=C2
|
||||
m=1
|
||||
value=16.384p
|
||||
footprint=1206
|
||||
device="ceramic capacitor"}
|
||||
C {capa.sym} 460 -260 2 0 {name=C4
|
||||
m=1
|
||||
value=10f
|
||||
footprint=1206
|
||||
device="ceramic capacitor"}
|
||||
C {capa.sym} 460 -180 0 0 {name=C3
|
||||
m=1
|
||||
value=10f
|
||||
footprint=1206
|
||||
device="ceramic capacitor"}
|
||||
C {gnd.sym} 460 -140 0 0 {name=l6 lab=GND}
|
||||
C {gnd.sym} 460 -300 2 0 {name=l7 lab=GND}
|
||||
C {devices/code_shown.sym} -395 -440 0 0 {name=MODEL1 only_toplevel=false
|
||||
format="tcleval( @value )"
|
||||
value="
|
||||
.lib cornerMOSlv.lib mos_tt_mismatch
|
||||
"}
|
||||
C {devices/code_shown.sym} 85 -930 0 0 {name=NGSPICE1 only_toplevel=false
|
||||
value="
|
||||
.control
|
||||
let run = 1
|
||||
let mc_runs = 400
|
||||
let results = unitvec(mc_runs)
|
||||
dowhile run <= mc_runs
|
||||
reset
|
||||
.param clock = 100e6 ; 100 MHz clock
|
||||
.param period = 1 / clock
|
||||
.param num_cycles = 100 ; number of evaluation cycles
|
||||
.param tr = num_cycles * period
|
||||
tran 300p 1u
|
||||
set run = $&run
|
||||
let vdiff = v(outp) - v(outm)
|
||||
|
||||
meas tran cross_time WHEN vdiff = 0.6
|
||||
let vindiff = v(vinp) - v(vbias)
|
||||
meas tran offset_voltage_\{$run\} find vindiff at=cross_time
|
||||
let results[$run - 1] = offset_voltage_\{$run\}
|
||||
let run = run + 1
|
||||
end
|
||||
print results > offset_MC_analysis.txt
|
||||
write offset_MC_analysis.raw
|
||||
.endc
|
||||
|
||||
"}
|
||||
|
|
@ -0,0 +1,120 @@
|
|||
import numpy as np
|
||||
import sys
|
||||
import os
|
||||
import matplotlib.pyplot as plt
|
||||
|
||||
SI_PREFIXES = {
|
||||
-9: "n", # nano
|
||||
-6: "µ", # micro
|
||||
-3: "m", # milli
|
||||
0: "", # base unit
|
||||
3: "k", # kilo
|
||||
6: "M", # Mega
|
||||
9: "G" # Giga
|
||||
}
|
||||
|
||||
def get_best_unit(value):
|
||||
if value == 0:
|
||||
return 0, ""
|
||||
exponent = int(np.floor(np.log10(abs(value)) / 3) * 3)
|
||||
exponent = max(min(exponent, 9), -9)
|
||||
unit = SI_PREFIXES.get(exponent, "")
|
||||
return exponent, unit
|
||||
|
||||
def format_value(value):
|
||||
exponent, unit = get_best_unit(value)
|
||||
return f"{value / (10**exponent):.6g} {unit}"
|
||||
|
||||
def calculate_histogram_data(file_path):
|
||||
results = []
|
||||
errors_removed = 0
|
||||
total_samples = 0
|
||||
|
||||
try:
|
||||
with open(file_path, 'r') as file:
|
||||
for line in file:
|
||||
if line.startswith("Index") or not line.strip():
|
||||
continue
|
||||
|
||||
try:
|
||||
_, result = line.split()
|
||||
value = float(result)
|
||||
total_samples += 1 # Count total samples
|
||||
|
||||
# Check if value is exactly 1.0000e+00
|
||||
if value == 1.0:
|
||||
errors_removed += 1
|
||||
continue # Skip this value
|
||||
|
||||
results.append(value)
|
||||
except ValueError:
|
||||
continue
|
||||
except Exception as e:
|
||||
print(f"Error reading the file: {e}")
|
||||
return [], 0, 0, errors_removed, total_samples
|
||||
|
||||
if errors_removed > 0:
|
||||
print(f"ERROR: There are {errors_removed} values out of bounds (equal to 1.0), data has been removed.")
|
||||
print(f"Total samples: {total_samples}, Remaining samples: {total_samples - errors_removed}")
|
||||
else:
|
||||
print(f"Total samples: {total_samples}")
|
||||
|
||||
mean = np.mean(results)
|
||||
std_dev = np.std(results)
|
||||
|
||||
print(f"Mean: {format_value(mean)}")
|
||||
print(f"Standard Deviation: {format_value(std_dev)}")
|
||||
|
||||
return results, mean, std_dev, errors_removed, total_samples
|
||||
|
||||
def create_histogram(results, mean, std_dev):
|
||||
script_directory = os.path.dirname(os.path.abspath(__file__))
|
||||
histogram_dir = os.path.join(script_directory, "histogram_plots")
|
||||
|
||||
if not os.path.exists(histogram_dir):
|
||||
os.makedirs(histogram_dir)
|
||||
|
||||
plt.style.use('seaborn-whitegrid')
|
||||
fig, ax = plt.subplots(figsize=(8, 6))
|
||||
|
||||
# Plot histogram
|
||||
bins = 30
|
||||
counts, bin_edges, _ = ax.hist(results, bins=bins, edgecolor='black', color='skyblue', alpha=0.7)
|
||||
|
||||
# Overlay individual data points as scatter dots
|
||||
bin_centers = (bin_edges[:-1] + bin_edges[1:]) / 2
|
||||
jitter = np.random.uniform(-0.1, 0.1, size=len(results)) # Adds slight randomness to prevent overlap
|
||||
ax.scatter(results, np.random.uniform(0, counts.max() * 0.1, len(results)),
|
||||
color='red', s=15, alpha=0.7, label=f"Mean: {format_value(mean)}\nStd Dev: {format_value(std_dev)}")
|
||||
|
||||
# Title and labels
|
||||
ax.set_title('Histogram of Results', fontsize=16, fontweight='bold')
|
||||
ax.set_xlabel('Results', fontsize=14)
|
||||
ax.set_ylabel('Frequency', fontsize=14)
|
||||
|
||||
# Grid settings
|
||||
ax.grid(True, linestyle='--', alpha=0.5)
|
||||
|
||||
# Set ticks for better readability
|
||||
ax.tick_params(axis='both', which='major', labelsize=12)
|
||||
|
||||
# Save figure
|
||||
histogram_path = os.path.join(histogram_dir, "histogram.png")
|
||||
plt.legend()
|
||||
plt.tight_layout()
|
||||
plt.savefig(histogram_path, dpi=300)
|
||||
print(f"Histogram saved to {histogram_path}")
|
||||
plt.close()
|
||||
|
||||
if __name__ == "__main__":
|
||||
if len(sys.argv) != 2:
|
||||
print("Usage: python script.py <path_to_txt_file>")
|
||||
else:
|
||||
file_path = sys.argv[1]
|
||||
|
||||
results, mean, std_dev, errors_removed, total_samples = calculate_histogram_data(file_path)
|
||||
|
||||
if results:
|
||||
generate_histogram = input("Do you want to create a histogram plot? (y/n): ").strip().lower()
|
||||
if generate_histogram == 'y':
|
||||
create_histogram(results, mean, std_dev)
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 201 KiB |
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Reference in New Issue