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luke / verilator
SystemVerilog 0 0
Verilator open-source SystemVerilog simulator and lint system
rtl verilog cpp compilers verilog-simulator verilator systemc system-verilog
Updated 2025-12-24 01:21:42 +01:00
luke / xschem
C 0 0
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Updated 2025-12-19 13:06:57 +01:00
luke / iverilog
C++ 0 0
Icarus Verilog
Updated 2025-12-17 04:55:50 +01:00
luke / netgen
C 0 0
Netgen complete LVS tool for comparing SPICE or verilog netlists
Updated 2025-12-12 08:00:03 +01:00
luke / sv2v
Haskell 0 0
SystemVerilog to Verilog conversion
verilog yosys systemverilog conversion
Updated 2025-11-24 01:25:07 +01:00
luke / UberDDR3
Verilog 0 0
Opensource DDR3 Controller
fpga verilog controller phy memory-controller ddr3-phy ddr3-controller ddr3
Updated 2025-06-14 05:52:13 +02:00
luke / manta
Python 0 0
A configurable and approachable tool for FPGA debugging and rapid prototyping.
fpga verilog icestorm icestick debug xilinx
Updated 2025-04-08 19:19:15 +02:00