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luke/ OpenRAM

Python 0 0 0

An open-source static random access memory (SRAM) compiler.

netlists netgen magic sram gds python ngspice

Updated 2026-08-16 19:01:32 +02:00

luke/ netgen

C 0 0 0

Netgen complete LVS tool for comparing SPICE or verilog netlists

Updated 2026-07-07 08:00:05 +02:00

luke/ prjpeppercorn

Python 0 0 0

Project Peppercorn - GateMate FPGA Bitstream Documentation

Updated 2026-06-16 14:07:15 +02:00

luke/ UberDDR3

Verilog 0 0 0

Opensource DDR3 Controller

fpga verilog controller phy memory-controller ddr3-phy ddr3-controller ddr3

Updated 2026-06-12 06:11:53 +02:00

luke/ ndk-fpga

0 0 0

Updated 2025-06-19 20:36:45 +02:00

luke/ icestorm

Python 0 0 0

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

Updated 2025-06-03 14:40:39 +02:00

luke/ cudd

Text 0 0 0

Updated 2024-02-10 14:21:36 +01:00