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luke/ verilator

SystemVerilog 0 0 0

Verilator open-source SystemVerilog simulator and lint system

rtl verilog cpp compilers verilog-simulator verilator systemc system-verilog

Updated 2026-09-08 17:08:34 +02:00

luke/ taxi

SystemVerilog 0 0 0

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

Updated 2026-08-28 22:34:16 +02:00