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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-29 01:24:25 +02:00
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v0.62
yosys/techlibs/intel/max10
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History
Richard Herveille 2893938355 Removed SystemVerilog module end label
2024-03-19 01:31:36 +01:00
..
cells_arith.v
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
cells_map.v
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
cells_sim.v
Removed SystemVerilog module end label
2024-03-19 01:31:36 +01:00
dsp_map.v
dsp_map for MAX10
2024-03-06 02:43:30 +01:00
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