yosys/backends at v0.62 - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-22 14:17:27 +02:00

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kamay e0077b188d Add gatesi_mode in BLIF format

2026-01-14 21:41:56 +01:00

..

Remove .c_str() calls from log()/log_error()

2025-09-11 20:59:37 +00:00

aiger2: fix case where submodule cell input port has empty SigSpec

2025-12-01 19:40:58 +01:00

Add gatesi_mode in BLIF format

2026-01-14 21:41:56 +01:00

write_btor: Include $assert and $assume cells in -ywmap output

2025-10-09 14:50:36 +02:00

Pass IdString by value instead of by const reference.

2025-12-22 01:52:59 +00:00

Remove unnecessary .c_str() in EDIF_ macros

2025-09-16 23:14:11 +00:00

Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix()

2025-09-16 23:02:16 +00:00

Fixes

2025-12-02 11:17:21 -08:00

Remove .c_str() calls from log()/log_error()

2025-09-11 20:59:37 +00:00

Remove .c_str() calls from log()/log_error()

2025-09-11 20:59:37 +00:00

Remove .c_str() calls from log()/log_error()

2025-09-11 20:59:37 +00:00

Merge pull request #5473 from YosysHQ/krys/unsized_params

2025-11-12 07:14:44 +13:00

Update backends to avoid bits()

2025-09-16 03:17:23 +00:00

Deliver more helpful error messages

2026-01-06 16:19:54 -08:00

Remove .c_str() calls from log()/log_error()

2025-09-11 20:59:37 +00:00

Remove .c_str() calls from log()/log_error()

2025-09-11 20:59:37 +00:00

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

write_verilog: Skip empty switches

2026-01-07 13:09:49 +13:00