Emil J. Tywoniak ff9cd0eed7 Makefile: test target requires unit-test, add vanilla-test for old test target

2026-02-09 23:21:24 +01:00

..

extending_yosys

Makefile: test target requires unit-test, add vanilla-test for old test target

2026-02-09 23:21:24 +01:00

flow

docs: fix verilog frontend internals

2025-08-11 13:34:10 +02:00

formats

rtlil: note SigSpec only has one chunk in internal docs

2025-11-10 12:08:35 +01:00

hashing.rst

pyosys: rewrite using pybind11

2025-10-03 11:54:44 +03:00

index.rst

Docs: Move verilog.rst to using_yosys

2025-08-05 09:53:58 +12:00

techmap.rst

Docs: Reflow line length

2024-10-15 07:23:45 +13:00