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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-05 03:32:09 +02:00
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yosys/tests/arch
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Eddie Hung 08221edbc1 tests: xilinx macc test to have initval, shorten BMC depth for runtime
2020-05-25 10:09:05 -07:00
..
anlogic
Simplify breaking tests/arch/*/fsm.ys tests
2020-03-20 11:25:17 -07:00
common
ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
2020-02-06 16:52:51 +00:00
ecp5
tests: remove write_ilang
2020-04-20 15:42:29 -07:00
efinix
Simplify breaking tests/arch/*/fsm.ys tests
2020-03-20 11:25:17 -07:00
gowin
Add opt_lut_ins pass. (#1673)
2020-02-03 14:57:17 +01:00
ice40
test: ice40_dsp test to read +/ice40/cells_sim.v for default params
2020-04-22 16:35:35 -07:00
intel_alm
intel_alm: direct LUTRAM cell instantiation
2020-05-07 21:03:13 +02:00
xilinx
tests: xilinx macc test to have initval, shorten BMC depth for runtime
2020-05-25 10:09:05 -07:00
run-test.sh
tests: extend tests/arch/run-tests.sh for defines
2020-03-05 08:08:32 -08:00
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