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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-04 03:23:11 +02:00
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ff785cdb46d6b1ddc19d5acc21b4d1236b3adf3f
yosys/techlibs/efinix
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Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes.
Fixes #2058.
2020-05-19 01:42:40 +02:00
..
arith_map.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
brams_map.v
one bit enable signal
2019-08-11 13:59:39 +02:00
brams.txt
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
cells_map.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
cells_sim.v
FF should be initialized to 0
2019-10-04 13:27:10 +02:00
efinix_fixcarry.cc
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
efinix_gbuf.cc
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
Makefile.inc
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
synth_efinix.cc
Get rid of dffsr2dff.
2020-04-15 16:22:37 +02:00
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