Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-01 18:47:29 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
ff28029fdb4fe97dca0e93b175dd2d6411671cb0
yosys/tests
T
History
Clifford Wolf 4af8d84f01 Small fix in tests/vloghtb/run-test.sh
2014-07-20 17:05:20 +02:00
..
asicworld
Added note to "make test": use git checkout of iverilog
2014-07-16 10:03:07 +02:00
hana
Added note to "make test": use git checkout of iverilog
2014-07-16 10:03:07 +02:00
memories
Added SAT-based write-port sharing to memory_share
2014-07-19 15:33:55 +02:00
realmath
Added note to "make test": use git checkout of iverilog
2014-07-16 10:03:07 +02:00
sat
now ignore init attributes on non-register wires in sat command
2014-07-05 11:18:38 +02:00
share
Added "miter -equiv -flatten"
2014-07-20 15:33:07 +02:00
simple
Implemented dynamic bit-/part-select for memory writes
2014-07-17 16:49:23 +02:00
techmap
Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface
2014-07-16 14:08:51 +02:00
tools
Also simulate unmapped memories in "make test"
2014-07-17 16:53:52 +02:00
vloghtb
Small fix in tests/vloghtb/run-test.sh
2014-07-20 17:05:20 +02:00
Powered by Gitea Version: 1.27.2 Page: 979ms Template: 3ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API