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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-05 19:36:55 +02:00
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fecafb2207efc772fec49b357bc6e20ca6a25aca
yosys/backends
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Eddie Hung fe0b421212 Output __const0__ and __const1__ CIs
2019-04-12 18:16:25 -07:00
..
aiger
Output __const0__ and __const1__ CIs
2019-04-12 18:16:25 -07:00
blif
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
btor
Add support for memory initialization to write_btor
2019-03-23 14:40:01 +01:00
edif
Fix "write_edif -gndvccy"
2019-03-01 12:59:07 -08:00
firrtl
Refine memory support to deal with general Verilog memory definitions.
2019-04-01 15:02:12 -07:00
ilang
Fix a syntax bug in ilang backend related to process case statements
2019-03-14 17:50:20 +01:00
intersynth
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
json
Merge pull request #591 from hzeller/virtual-override
2018-08-15 14:05:38 +02:00
protobuf
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
simplec
Fix typographical and grammatical errors and inconsistencies.
2019-01-02 13:12:17 +00:00
smt2
Fix smtbmc.py handling of zero appended steps
2019-03-14 22:04:42 +01:00
smv
Minor update
2018-10-15 13:54:12 -04:00
spice
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
table
Fix typographical and grammatical errors and inconsistencies.
2019-01-02 13:12:17 +00:00
verilog
Improve determinism of IdString DB for similar scripts
2019-03-11 20:12:28 +01:00
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