Clifford Wolf d9a2b43014 Add $dlatch support to write_verilog ...

Signed-off-by: Clifford Wolf <[email protected]>

2018-04-22 16:03:26 +02:00

..

aiger

Fix generation of multiple outputs for same AIG node in write_aiger

2017-07-05 14:23:54 +02:00

blif

Add "write_blif -inames -iattr"

2018-04-15 14:07:21 +02:00

btor

Add "no driver for signal bit" error msg to btor back-end

2017-12-24 17:30:36 +01:00

edif

Fix the fixed handling of x-bits in EDIF back-end

2017-07-11 17:45:29 +02:00

firrtl

More progress on Firrtl backend.

2017-02-13 11:17:53 -08:00

ilang

Fixed gcc 7.2 "statement will never be executed" warning

2018-02-03 14:31:47 +01:00

intersynth

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

json

Add attributes and parameter support to JSON front-end

2017-07-10 13:17:38 +02:00

simplec

Add workaround for CBMC bug to SimpleC back-end

2017-05-17 21:07:54 +02:00

smt2

Add smtio.py support for parsing SMT2 (_ bvX n) syntax for BitVec constants

2018-04-04 18:12:27 +02:00

smv

Add $_ANDNOT_ and $_ORNOT_ gates

2017-05-17 09:08:29 +02:00

spice

Also escape "=" in spice output

2016-05-20 16:43:13 +02:00

table

Add write_table command

2017-07-05 12:13:53 +02:00

verilog

Add $dlatch support to write_verilog

2018-04-22 16:03:26 +02:00