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luke
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fe3adfd960d97ea7ef762efd082346494a9d8c35
yosys
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techlibs
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quicklogic
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common
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N. Engelhardt
98769010af
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
..
cells_sim.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00