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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00
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fe3a932cfa17c835f5e400c8fc8411635ba0c997
yosys/techlibs/greenpak4
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Andrew Zonenberg fe3a932cfa Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital
2017-08-14 10:45:39 -07:00
..
cells_latch.v
greenpak4: Can now techmap inferred D latches (without set/reset or output inverter)
2016-12-10 18:46:36 +08:00
cells_map.v
Initial implementation of techlib support for GreenPAK latches. Instantiation only, no behavioral inference yet.
2016-12-05 21:22:41 -08:00
cells_sim_ams.v
Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital
2017-08-14 10:45:39 -07:00
cells_sim_digital.v
Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital
2017-08-14 10:45:39 -07:00
cells_sim.v
Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital
2017-08-14 10:45:39 -07:00
gp_dff.lib
Fixed indenting in techlibs/greenpak4/gp_dff.lib
2016-03-29 13:44:14 +02:00
greenpak4_counters.cc
greenpak4_counters: Changed generation of primitive names so that the absorbed register's name is included
2017-06-24 14:54:07 -07:00
greenpak4_dffinv.cc
greenpak4: Added support for inferred input/output inverters on latches
2016-12-10 19:58:32 +08:00
Makefile.inc
Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital
2017-08-14 10:45:39 -07:00
synth_greenpak4.cc
Fix double-call of log_pop() in synth_greenpak4
2017-02-14 11:57:54 +01:00
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