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yosys/tests/proc
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Gary Wong 7b09dc31af tests: add cases covering full_case and parallel_case semantics 
This is @KrystalDelusion's suggestion in PR #5141 to verify
sensible implementation of all 4 possible full_case/parallel_case
combinations.

(Also including two similar tests to check the Verilog frontend
applies the correct attributes when given SystemVerilog
priority/unique case and if statements.)
2025-05-29 20:45:57 -06:00
..
.gitignore
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
bug2619.ys
proc_dff: Fix emitted FF when a register is not assigned in async reset
2021-03-08 17:01:43 +01:00
bug2656.ys
proc_arst: Add special-casing of clock signal in conditionals.
2021-03-15 17:17:29 +01:00
bug2962.ys
Remove references to ilang
2024-11-05 12:36:31 +13:00
bug4712.ys
tests/proc: add proc_dff bug 4712 as testcase
2024-11-07 00:10:17 +01:00
bug_1268.v
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
bug_1268.ys
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
case_attr.ys
tests: add cases covering full_case and parallel_case semantics
2025-05-29 20:45:57 -06:00
clean_undef_case.ys
proc_clean: only consider fully-defined switch operands too.
2023-08-12 02:46:31 +02:00
proc_dff.ys
proc_dff: add tests
2024-08-28 16:24:47 +01:00
proc_rom.ys
Remove references to ilang
2024-11-05 12:36:31 +13:00
rmdead.v
proc_rmdead: use explicit pattern set when there are no wildcards
2021-07-29 20:55:59 -04:00
rmdead.ys
proc_rmdead: use explicit pattern set when there are no wildcards
2021-07-29 20:55:59 -04:00
run-test.sh
tests: use /usr/bin/env for bash.
2023-08-12 11:59:39 +10:00