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Gary Wong 5feb1a1752 verilog: add support for SystemVerilog string literals. 
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-07-03 20:51:12 -06:00
..
extending_yosys
Reinstate #4768
2025-04-08 11:58:05 +12:00
flow
docs: several small documentation fixes.
2025-05-29 21:26:28 -06:00
formats
Docs: Move rtlil_text (back) to appendix
2024-10-15 07:34:52 +13:00
hashing.rst
hashlib: document merged hash_top_ops with hash_ops
2025-01-20 16:25:52 +01:00
index.rst
Docs: Formatting and fixes
2024-12-18 14:58:51 +01:00
techmap.rst
Docs: Reflow line length
2024-10-15 07:23:45 +13:00
verilog.rst
verilog: add support for SystemVerilog string literals.
2025-07-03 20:51:12 -06:00