luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 18:13:40 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
fdff32dd731d92c854aef73ea9fad89635e82c0f
yosys/techlibs/anlogic
T
History
Icenowy Zheng 1b36944299 anlogic: add latch cells 
Add latch cells to Anlogic cells replacement library by copying other
FPGAs' latch code to it.

Signed-off-by: Icenowy Zheng <[email protected]>
2018-12-25 22:47:46 +08:00
..
anlogic_eqn.cc
Initial support for Anlogic FPGA
2018-12-01 18:28:54 +01:00
arith_map.v
Initial support for Anlogic FPGA
2018-12-01 18:28:54 +01:00
cells_map.v
anlogic: add latch cells
2018-12-25 22:47:46 +08:00
cells_sim.v
Initial support for Anlogic FPGA
2018-12-01 18:28:54 +01:00
drams_map.v
anlogic: add support for Eagle Distributed RAM
2018-12-17 23:20:40 +08:00
drams.txt
anlogic: fix dbits of Anlogic Eagle DRAM16X4
2018-12-18 14:38:44 +08:00
eagle_bb.v
Revert "Leave only real black box cells"
2018-12-17 23:20:40 +08:00
Makefile.inc
anlogic: fix Makefile.inc
2018-12-19 10:23:58 +08:00
synth_anlogic.cc
Anlogic: let LUT5/6 have more cost than LUT4-
2018-12-19 09:36:53 +08:00