This website requires JavaScript.
Explore
Help
Sign In
luke
/
yosys
Watch
1
Star
0
Fork
0
mirror of
https://github.com/YosysHQ/yosys.git
synced
2026-09-06 11:59:46 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
fdf7c421810e8718f7ee312ddd3cfdbfb65aa2ce
yosys
/
tests
/
lut
T
History
whitequark
c38ea9ae65
equiv_opt: new command, for verifying optimization passes.
2018-12-07 17:20:34 +00:00
..
.gitignore
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
2018-12-05 17:13:27 +00:00
check_map.ys
equiv_opt: new command, for verifying optimization passes.
2018-12-07 17:20:34 +00:00
map_and.v
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
2018-12-05 17:13:27 +00:00
map_mux.v
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
2018-12-05 17:13:27 +00:00
map_not.v
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
2018-12-05 17:13:27 +00:00
map_or.v
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
2018-12-05 17:13:27 +00:00
map_xor.v
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
2018-12-05 17:13:27 +00:00
run-test.sh
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
2018-12-05 17:13:27 +00:00
