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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-29 01:24:25 +02:00
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fdafb74eb77e33e9fa2b4e591804d1d02c122ff9
yosys/techlibs/ice40
T
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Eddie Hung fdafb74eb7 kernel: use more ID::*
2020-04-02 07:14:08 -07:00
..
tests
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
2019-08-12 12:06:45 -07:00
.gitignore
…
abc9_model.v
ice40: specify fixes
2020-02-27 10:17:29 -08:00
arith_map.v
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
2020-01-24 11:59:48 -08:00
brams_init.py
…
brams_map.v
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
2019-02-28 16:23:40 -08:00
brams.txt
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
cells_map.v
xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
2020-01-27 13:30:27 -08:00
cells_sim.v
ice40: Fix typos in SPRAM ABC9 timing specs
2020-03-20 22:19:55 +01:00
dsp_map.v
Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing
2019-08-08 12:56:05 -07:00
ice40_braminit.cc
substr() -> compare()
2019-08-07 12:20:08 -07:00
ice40_ffinit.cc
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
ice40_ffssr.cc
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
ice40_opt.cc
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
latches_map.v
Added synth_ice40 support for latches via logic loops
2016-05-06 23:02:37 +02:00
Makefile.inc
ice40: move over to specify blocks for -abc9
2020-02-27 10:17:29 -08:00
synth_ice40.cc
Fix indentation in techlibs/ice40/synth_ice40.cc.
2020-04-01 16:29:56 +00:00
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