mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-09-05 11:35:20 +02:00
11 lines
252 B
Verilog
11 lines
252 B
Verilog
module dffsr_mixedpol(input CLK, D, CLEAR, PRESET, output reg Q, output QN);
|
|
|
|
always @(posedge CLK, negedge CLEAR, posedge PRESET)
|
|
if (PRESET) Q <= 1'b1;
|
|
else if (~CLEAR) Q <= 1'b0;
|
|
else Q <= ~D;
|
|
|
|
assign QN = ~Q;
|
|
|
|
endmodule
|